Intel Corporation

Eric K Mann

Patrick L Connor

Anil Vasudevan

Daniel Todd Cohn

Parthasarathy Sarangam

Manasi Deval

Cong Li

Anjaneya Reddy Chagam Reddy

Muralidhar Rajappa

Ramkumar Nagappan

Raed Kanjo

Jim Daubert

David Wescott

David M Durham

Tsung-Yuan Charles Tai

Ren Wang

Paul S Diefenbaugh

Christian Maciocco

Jr-Shian Tsai

Eugene Gorbatov

Devadatta V Bodas

Sameh Gobriel

Nimrod Diamant

Reuven Rozic

Priya Govindarajan

Hieu Trung Tran

Chun Yang Chiu

John P Jacobs

Gary D Gumanow

Devices and techniques for reorder resilient transport are described herein. A device may store data packets in sequential positions of a flow queue in an order in which the data packets were received. The device may retrieve a first data packet from a first sequential position and a second data packet from a second sequential position that is next in sequence to the first sequential position in the flow queue. The device may store the first data packet and the second data packet in a buffer and refrain from providing the first data packet and the second data packet to upper layer circuitry if the packet order information for the first data packet and the second data packet indicate that the first data packet and the second data packet were received out of order. Other embodiments are also described.

Reorder resilient transport

Examples are disclosed for determining or using server transaction latency information. In some examples, a network input/output device coupled to a server may be capable of time stamping information related to ingress request and egress response packets for a transaction. For these examples, elements of the server may be capable of determining transaction latency values based on the time stamped information. The determined transaction latency values may be used to monitor or manage operating characteristics of the server to include an amount of power provided to the server or an ability of the server to support one or more virtual servers. Other examples are described and claimed.

Techniques associated with server transaction latency information

Methods and apparatus for facilitating efficient Quality of Service (QoS) support for software-based packet processing by offloading QoS rate-limiting to NIC hardware. Software-based packet processing is performed on packet flows received at a compute platform, such as a general purpose server, and/or packet flows generated by local applications running on the compute platform. The packet processing includes packet classification that associates packets with packet flows using flow IDs, and identifying a QoS class for the packet and packet flow. NIC Tx queues are dynamically configured or pre-configured to effect rate limiting for forwarding packets enqueued in the NIC Tx queues. New packet flows are detected, and mapping data is created to map flow IDs associated with flows to the NIC Tx queues used to forward the packets associated with the flows.

Efficient QoS support for software packet processing on general purpose servers

An embodiment may include circuitry that may generate and/or use, at least in part, at least one descriptor to be associated with at least one packet. The at least one descriptor may specify at least one transmission time at which the at least one packet is to be transmitted. The at least one transmission time may be specified in the at least one descriptor in such a manner as to permit the at least one transmission time to be explicitly identified based at least in part upon the at least one descriptor. Many alternatives, modifications, and variations are possible without departing from this embodiment.

Circuitry to generate and/or use at least one transmission time in at least one descriptor

A method and system for managing a power state of a processor are described herein. The method includes receiving, at the processor, a signal indicating that an interrupt is to be sent to the processor. The method also includes transitioning the processor from the deep idle state to the shallow idle state in response to receiving the signal and transitioning the processor from the shallow idle state to an active state in response to receiving the interrupt.

Managing a power state of a processor

Methods and systems may provide for determining a plurality of buffer-related settings for a corresponding plurality of idle states and outputting the plurality of buffer-related settings to a device on a platform. The device may determine an observed bandwidth for a channel associated with a receive buffer and identify a selection of a buffer-related setting from the plurality of buffer-related settings based at least in part on the observed bandwidth. In one example, each buffer-related setting includes a latency tolerance and a corresponding idle duration.

Intelligent receive buffer management to optimize idle state residency

In an embodiment, a method is provided. The method of this embodiment provides in response to receiving a packet, determining a packet tuple; generating a hash result by performing a commutative hash function on the packet tuple; and processing the packet on one of a plurality of processors based, at least in part, on the hash result.

Bidirectional receive side scaling

A technique to process interrupts on a virtualized platform. A plurality of virtual machines (VMs) runs on the virtualized platform having at least a processor. The VMs include a power VM. A VM scheduler schedules the VMs for execution on the virtualized platform according a scheduling policy. A virtualized interrupt mask controller controls masking an interrupt from an interrupting source according to the scheduling policy. An interrupt is masked from an interrupting source according to the scheduling policy for at least one of the VMs; and the at least one of the VMs is caused to get the interrupt when the at least one of the VMs is enabled according to the scheduling policy.

Interrupt processing on virtualized platform during periods which virtual machines are enabled to get interrupts according to scheduling policy

An embodiment of the present invention is a technique to tag network transactions. A virtual queue stores packets received from and transmitted to a network interface card (NIC). A global session manager manages packet communication with a capability operating system (COS). A global virtual machine (VM) database stores global session identifiers (SIDs) of the packets and associated metadata. The global SIDs are used by the global session manager to track network sessions. The metadata describe characteristics of session connections. A VM tunnel connection encapsulates the packets passing to and from the COS.

Tagging network I/O transactions in a virtual machine run-time environment

A technique to process interrupts on a virtualized platform. A plurality of virtual machines (VMs) runs on the virtualized platform having at least a processor. The VMs include a power VM. A VM scheduler schedules the VMs for execution on the virtualized platform according a scheduling policy. A virtualized interrupt mask controller controls masking an interrupt from an interrupting source according to the scheduling policy.

Time sliced interrupt processing on virtualized platform

Provided are a method, system, and article of manufacture for managing network throughput. An application identifies at least one network connection of a plurality of network connections, wherein packets arriving via the one network connection require greater resources at a computational device relative to resources required by other network connections. The application determines if resources required at the computational device by the plurality of network connections exceed a threshold and eliminates the at least one network connection to the computational device.

Method, system, and article of manufacture for increasing network throughput

Provided are a method, system and article of manufacture for adjusting interrupt levels. A current system interrupt rate at a computational device is determined, wherein the current system interrupt rate is a sum of interrupt rates from a plurality of interrupt generating agents. The current system interrupt rate is compared with at least one threshold interrupt rate associated with the computational device. Based on the comparison, an interrupt moderation level is adjusted at an interrupt generating agent of the plurality of interrupt generating agents.

Method, system, and article of manufacture for adjusting interrupt levels

An arrangement is provided for ingress processing optimization via traffic classification and grouping. A plurality of packets are classified according to a classification criterion. The classified packets are used to generate a packet bundle containing packets that are uniform with respect to the classification criterion. The packet bundle and its corresponding packet bundle descriptor are transferred to a host which then processes the packet bundle as a whole according to the information contained in the packet bundle descrptor.

Growing community of inventors

Hillsboro, OR, United States of America

Eric K Mann