Qorvo Us, Inc.

Rf Micro Devices, Inc.

Mstar Semiconductor, Inc.

Cypress Semiconductor Corporation

Mstar France Sas

Mstar Software R&d (shenzhen) Ltd.

Mstar Semiconductor, Inc. (cayman Islands)

Eric K Bolton

Daniel Charles Kerr

Baker P Scott

Christian Rye Iversen

George Adrian Maxim

Dirk Robert Walter Leipold

Hideya Oshima

Robert Andrew Phelps

Nadim Khlat

Marcus Granger-Jones

Alexander Wayne Hietala

Ruediger Bauder

Christopher Truong Ngo

David E Reed

Steven C Meyers

Francesc Boixadera

Stuart Bennett

A multi-mode antenna tuner circuit and related apparatus are provided. The multi-mode antenna tuner circuit can be configured to operate in a low-current mode or a high-power mode. When operating in the high-power mode, the multi-mode antenna tuner circuit can provide full-fledged functionalities and consume a higher amount of current. In contrast, in the low-current mode, the multi-mode antenna tuner circuit provides reduced functionality and consumes a lower amount of current. In this regard, in a wireless communication apparatus employing multiple multi-mode antenna tuner circuits, it is possible to opportunistically configure some multi-mode antenna tuner circuits to operate in the low-current mode based on an operating environment (e.g., frequency band, location, etc.) and internal state (e.g., battery level, signal strength, etc.) of the wireless communication apparatus. As a result, it may be possible to reduce consumption and heat dissipation without compromising performance of the wireless communication apparatus.

Multi-mode antenna tuner circuit and related apparatus

Systems and methods for antenna impedance matching provide an integrated circuit (IC) configured to be placed proximate an antenna that includes a sensor based on a coupler having forward and reverse power detectors for detecting an impedance at the antenna and provides dynamic impedance matching. Further, exemplary aspects of the present disclosure contemplate using a single wire bus capable of supplying power and providing a bidirectional serial communication link to allow communication between the IC of the present disclosure and a control circuit (e.g., a bridge or transceiver). Further aspects of the present disclosure contemplate providing systems and methods for calibrating the IC at production. Further, the accuracy of the impedance sensor may be dependent on accurate determination of power and phase difference between forward and reverse coupled signals, and a system for removing an offset between the forward and reverse power detectors is disclosed.

Systems and methods for antenna impedance matching

An overvoltage detector for an RF switch is disclosed. The overvoltage detector is made up of circuitry having a detector output that couples to a controller, a body voltage input that couples to a charge pump, and a body voltage output that couples to a body terminal of the RF switch. The overvoltage detector is configured to detect an overvoltage across the RF switch by monitoring body leakage current flowing between the body voltage input and the body voltage output. Upon detecting body leakage current over a predetermined level, the overvoltage detector generates an overvoltage signal at the detector output to indicate an overvoltage across the RF switch.

Overvoltage detector for an RF switch

A first stacked RF switch, which operates in one of an ON mode and an OFF mode, and includes a group of RF switching circuits coupled in series between a first RF switch connection node and a second RF switch connection node, is disclosed. The group of RF switching circuits includes a first RF switching circuit, which includes a first switching transistor element coupled between a first source connection node and a first drain connection node, a first source/drain (S/D) bias resistive element coupled across the first switching transistor element, and a first S/D shorting circuit coupled across the first S/D bias resistive element. During the ON mode, the first switching transistor element is ON and the first S/D shorting circuit is ON. During a first interval immediately following a transition from the ON mode to the OFF mode, the first S/D shorting circuit is ON.

Stacked RF switch with fast switching speed

Improved Radio Frequency (RF) switches are provided herein. According to one aspect, an RF switch comprises one or more stages. In one embodiment, each stage comprises a signal input terminal, a signal output terminal, a control input terminal, and a switching device having a first terminal connected to the signal input terminal, a second terminal connected to the signal output terminal, and a third terminal for controlling the on/off state of the switching device. Each stage includes a first resistor connected in series between the control input terminal and the third terminal, a first bypass switch for electrically bypassing the first resistor, and a second resistor connected in series between the signal input terminal and the signal output terminal. The first resistors form a first bias network, the second resistors form a second bias network, and the switching devices are connected in series.

RF branch with accelerated turn-on and high Q value

A Radio Frequency (RF) switch having two or more stages coupled in series is disclosed. A first Field-Effect Transistor (FET) with a first control terminal is coupled across a gate resistor to shunt the gate resistor when the first FET is on. An RF switching device is configured to pass an RF signal between a signal input and a signal output when the RF switching device is on. A second FET having a second control terminal coupled to an acceleration output is configured to shunt the RF switching device when the second FET is on. A third FET is coupled between the first control terminal and the signal input for controlling charge on a gate of the first FET. A third control terminal of the third FET is coupled to an acceleration input for controlling an on/off state of the third FET.

Radio frequency (RF) switch with on and off switching acceleration

Antenna tuning circuitry includes an antenna tuning node, an antenna tuning switch, and a resonant tuning circuit. The antenna tuning node is coupled to a resonant conduction element of an antenna. The antenna tuning switch and the resonant tuning circuit are coupled in series between the antenna tuning switch and the antenna tuning node, such that the resonant tuning circuit is between the antenna tuning node and the antenna tuning switch. The resonant tuning circuit is configured to resonate at one or more harmonic frequencies generated by the antenna tuning switch such that a high impedance path is formed between the antenna tuning switch and the antenna tuning node at harmonic frequencies generated by the antenna tuning switch. Accordingly, harmonic interference generated by the antenna tuning switch is prevented from reaching the antenna, while simultaneously allowing for tuning of the antenna.

Antenna tuning circuitry with reduced interference

Disclosed is a digital communication control system having a serial bus buffer that includes a primary interface adapted to support serial communication over a primary bus, a buffered interface adapted to support serial communication over a buffered bus, and a controller coupled between the primary bus and the buffered bus. The primary bus is coupled to a first device and at least one second device and the buffered bus is coupled to at least one third device. The controller is adapted to receive a first data signal and a clock signal at the primary interface and replicate the first data signal and the clock signal at the buffered interface.

Serial bus buffer with noise reduction

An apparatus, which includes a first electronic device, a first nonlinear capacitance compensation circuit, and a capacitance compensation control circuit, is disclosed. The first electronic device has a first nonlinear capacitance and is coupled to the first nonlinear capacitance compensation circuit, which has a first compensation capacitance and receives a first compensation control signal. The capacitance compensation control circuit adjusts the first compensation capacitance using the first compensation control signal to at least partially linearize the first nonlinear capacitance.

Nonlinear capacitance linearization

Disclosed is a harmonic cancellation circuit for an RF switch branch having a first transistor with a first gate terminal and a first body terminal, a second transistor having a second gate terminal coupled to the first body terminal, and having a second body terminal coupled to the first gate terminal. Also included is a first resistor coupled between a first coupling node and the second body terminal, and a second resistor coupled between a second coupling node and the first body terminal, wherein the first transistor and second transistor are adapted to generate an inverse phase third harmonic signal relative to a third harmonic signal generated by the RF switch branch, such that the inverse phase third harmonic signal is output through the first resistor and the second resistor to the RF switch branch to reduce the third harmonic signal.

Harmonic cancellation circuit for an RF switch branch

RF switching circuitry includes an RF switch coupled between an input node and an output node. Distortion compensation circuitry is coupled in parallel with the RF switch between the input node and the output node. The RF switch is configured to selectively pass an RF signal from the input node to the output node based on a first switching control signal. The distortion compensation circuitry is configured to boost a portion of the RF signal that is being compressed by the RF switch when the amplitude of the RF signal is above a predetermined threshold by selectively injecting current into one of the input node or the output node. Boosting a portion of the RF signal that is being compressed by the RF switch allows a signal passing through the RF switch to remain substantially linear, thereby improving the performance of the RF switching circuitry.

Technique to reduce the third harmonic of an on-state RF switch

Embodiments of techniques for low-cost multimode operation in wireless communications involving the Time Division Synchronous Code Division Multiple Access (TD-SCDMA) standard and the Global System for Mobile telecommunications (GSM) standard are described. In one aspect, a method of multimode operation in a mobile telecommunication device renders wireless communications based on the TD-SCDMA standard using either or both of first and second frequency synthesizers of the mobile telecommunication device. The method also receives signals based on the GSM standard using either or both of the first and second frequency synthesizers of the mobile telecommunication device. Techniques for performing baton handover as well as signal reception for multimedia broadcast and multicast services (MBMS) using two frequency synthesizers are also provided.

Low-cost multimode GSM monitoring from TD-SCDMA

The present invention discloses a continuous voltage controlled oscillator (VCO) frequency temperature compensation apparatus for a phase locked loop (PLL) and a continuous VCO frequency temperature compensation method for a PLL. The system utilizes a VCO with one digital coarse tuning input, a first analog fine tuning input, and a second analog fine tuning input. The system uses the second analog fine tuning inputs to compensate the VCO for frequency shifts due to temperature fluctuation. When the PLL transitions to the fine lock (FL) mode, the system starts driving the second fine tuning input with a differential amplifier. The differential amplifier compares the first fine tuning input with a reference voltage, and drives the second fine tuning input to compensate the first fine tuning input.

VCO frequency temperature compensation system for PLLs

A self-biasing negative transconductance LC oscillator that uses self-biasing circuitry to regulate a current source that feeds negative transconductance circuitry and direct current (DC) bias circuitry to apply a DC bias between control inputs and outputs of the negative transconductance circuitry is disclosed. A current source setpoint is based on the voltage swing of the oscillator, which can then be controlled by the DC power supply that powers the oscillator. In one embodiment of the present invention, the negative transconductance circuitry includes a pair of p-type metal oxide semiconductor (PMOS) cross-coupled field effect transistors (FETs), which have a limit applied to their gate to source voltages. Limiting the gate to source voltages of the FETs limits the percentage of the oscillation cycle that the FETs spend in the triode region and thus reduces the noise contribution of the FETs and allows for less power consumption for a given noise requirement.

Self-biasing low-phase noise LC oscillator

A charge pump circuit with resistively attenuated inputs is described herein. By reducing a voltage swing of input signals supplied thereto, the charge pump circuit described herein is configured for producing output signals with relatively low static phase offset even when operating at relatively low power supply voltages (e.g., less than about 1.2 volts). In general, the input voltage swing may be reduced by coupling an attenuator to each input of the charge pump circuit. A method for operating the differential charge pump is described, along with exemplary devices (e.g., PLL and DLL devices) within which the charge pump may be utilized.

Growing community of inventors

Kernersville, NC, United States of America

Eric K Bolton