Silicon Laboratories Inc.

Ambiq Micro, Inc.

Conexant Systems, Inc.

Eric Jonathan Deal

Stephen James Sheafor

Daniel Martin Cermak

Donovan Scott Popps

Mark Willard Johnson

Matthew Brandon Gately

Mark A Baur

Scott McLean Hanson

Daniel Thomas Riedler

Sebastian Ahmed

Junkang Ren

Scott McLean

An apparatus includes a pipelined processor. The pipelined processor includes a pipeline and a hardware fence. The hardware fence detects if a hazard condition exists by comparing an address for an input operation with an address for an output operation.

Apparatus for processor with hardware fence and associated methods

An apparatus includes an array processor to process array data in response to information contained in a packet, wherein the packet comprises a set of fields specifying configuration information for processing the array.

Apparatus for array processor with program packets and associated methods

An apparatus includes an array processor to process array data in response to a set of macro-instructions. A macro-instruction in the set of macro-instructions performs loop operations, array iteration operations, and/or arithmetic logic unit (ALU) operations.

Processor with macro-instruction achieving zero-latency data movement

An apparatus includes an array processor to process at least one array. The apparatus further includes a memory coupled to the array processor. The at least one array is stored in memory with programmable per-dimension size and stride values.

Array processor using programmable per-dimension size values and programmable per-dimension stride values for memory configuration

An apparatus includes an array processor to process array data. The array data are arranged in a memory. The array data are specified with programmable per-dimension size and stride values.

Array processor having an instruction sequencer including a program state controller and loop controllers

A microcontroller system includes a processing unit supporting at least one near or sub Vt circuit and a plurality of memory blocks, each memory block connected to a DMA controller and independently power controlled. A power control system uses power gates to power control at least the memory blocks. In some embodiments, a wake-up interrupt controller is connected to the power control system and a voltage regulator system is used to supply voltage to separate power domains, with the voltage regulator systems controlled at least in part by power gates operated by the power control system. A plurality of clocks can be connected to define clock domains associated with separate power domains.

Very low power microcontroller system

A communication system for transferring (Peripheral Component Interconnect) PCI and non-PCI data over a non-PCI bus is disclosed. The system bus is a non-PCI bus having an address bus and a data bus for communicating addresses and data. A PCI-compatible peripheral is coupled to the non-PCI bus for transmitting and receiving PCI-compatible data. A non-PCI device is also coupled to the non-PCI bus for transmitting and receiving non-PCI data. In addition, a slave device is also coupled to the non-PCI bus for receiving and transmitting non-PCI data and PCI data. A byte size control line capable of being driven by the PCI-compatible peripheral and the non-PCI device is coupled between the PCI-compatible peripheral, the non-PCI device, and the slave device for indicating whether data appearing on the data bus is from the PCI-compatible peripheral or the non-PCI device, and for indicating how many bytes on the data bus are actually valid, if the data appearing on the non-PCI bus is from the non-PCI device. A bus byte enable (BBE) driven by the PCI-compatible peripheral is also coupled between the PCI-compatible peripheral and the slave device for indicating which bytes on the data bus are valid. The slave device decodes the byte size control line, the BBE, and the address bus to accept valid bytes of PCI-compatible data and non-PCI data appearing on the data bus.

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Austin, TX, United States of America

Eric Jonathan Deal