Broadcom Corporation

Avago Technologies General IP (singapore) Pte. Ltd.

Eric John Spada

Wael William Diab

Yongbum Kim

Fong Pong

Patricia Ann Thaler

Brian David Petry

Karen Marie Schramm

Stephen Anderson

Scott Winterble

Fault tolerant and redundant grand master clock scheme may reduce or eliminate precision time transition caused by a network link or device failure. A primary synchronization message may be sent by a primary grandmaster clock and one or more backup synchronization message may be sent by respective backup grandmaster clocks. The primary and backup grandmaster clocks may be concurrently operated. The primary and backup synchronization messages may be sent to an end station over a network. The end station may derive a local clock based on one, some, or all of the received messages. The end station may or may not distinguish between the messages based on the clock source. The end station may validate messages received from a particular clock source.

Fault tolerant clock network

Devices implement encapsulation to support link layer preemption. The device may include a encapsulation logic that encapsulates data, such as an Ethernet frame, to produce an encapsulated frame. The encapsulated frame may include an encapsulation element that indicates whether the encapsulated data includes non-preemptible data, such as Distinguished Minimum Latency Traffic (DMLT), or preemptible data. The encapsulated frame may also indicate whether the encapsulated data comprises the last fragment of a preemptible frame.

Encapsulation for link layer preemption

A memory access circuit and a corresponding method are provided. The memory access circuit includes a crypto block in communication with a memory that encrypts data of a data block on a block basis. The memory access circuit also includes a fault injection block configured to inject faults to the data in the data block. The memory access circuit further includes a data scrambler and an address scrambler. The data scrambler is configured to scramble data in the memory by shuffling data bits within the data block in a plurality of rounds and mash the shuffled data bits with random data. The address scrambler is configured to distribute the scrambled data across the memory. A memory system including the memory access circuit is also disclosed to implement the corresponding method.

Secure memory access controller

A method and system for network offloading includes receiving a packet at a communication interface of a wireless access point and processing the packet at a flow acceleration processor prior to processing the packet at a host processor. The flow acceleration processor may process the packet for header checking or security processing. The flow acceleration processor may provide the packet to a security coprocessor for security processing. The flow acceleration processor may generate a result code indicating whether the processing at the flow acceleration processor was successful. If the processing was unsuccessful, the packet is provided to the host processor for exception processing.

Tunnel acceleration for wireless access points

A system and method for enabling energy efficient Ethernet networks with time-sensitive protocols. Time-stamped packets generated by a time-sensitive protocol rely on fixed latency in a transit time through a transmission subsystem. An energy efficiency control policy in a network device governs a transmission of time-stamped packets in accordance with energy efficiency initiatives controlled by the energy efficiency control policy. In one embodiment, time-stamped packets can be dropped or modified to account for transitions by the transmission subsystem into an energy saving state. In another embodiment, transitions by the transmission subsystem into or out of an energy saving state can be impacted by the existence of time-stamped packets scheduled for transmission.

Growing community of inventors

Groton, MA, United States of America

Eric John Spada