Infineon Technologies Ag

Siemens Aktiengesellschaft

Cisco Technology, Inc.

Infineon Technologies North America Corp.

Eric John Chesters

Rod G Fleck

Klaus Oberlaender

Ralph W Haines

Dirk Behrens

Venkat Mattela

Roger D Arnold

John Joseph Williams, Jr

Vojin G Oklobdzija

Muhammad Afsar

Bruce Holmer

Andreas Wenzel

Balraj Singh

Gary Sheedy

A configurable processor architecture uses a common simulation database for multiple processor configurations to reduce the cost of producing customized processor configurations. An unchanging core portion is used in each processor configuration. To support different memory modules, identification signals are provided from the memory modules or an identification module to configure the core portion.

Configurable embedded processor

Disclosed are, inter alia, methods, apparatus, computer-storage media, mechanisms, and means associated with cooperative flow locks distributed among multiple components, such as on different application-specific integrated circuits in a packet switching device. Flow locks are typically used for maintaining the order of packets and operations performed thereon by the coordination of a context (e.g., the processing of a packet by a packet processor) with a corresponding flow lock interface, and by the manner of communication performed among the flow lock interface and the distributed flow locks.

Cooperative flow locks distributed among multiple components

An on-chip debug system includes a data band selector operable to transmit to an emulator the selected data bands generated by the selected components in an integrated circuit. The data band selector is directed by the emulator based upon instructions received from a host computer.

On-chip debug system

A method and an apparatus for reducing the number of instruction transactions in a microprocessor are disclosed. As a method, the number of issued instructions carried by an issued instruction bus in a computer system are reduced by determining if an instruction fetched by a fetch unit matches a cached instruction tag. When the fetched instruction matches the cached instruction tag, an opcode and an associated instruction corresponding to the cached instruction tag are directly injected to an appropriate function unit. The apparatus includes a plurality of tag PC cache memory devices used to store tag PC entries associated with target instructions injected directly to corresponding function units included microprocessors and the like. The injection reduces the number of instructions fetched from the program memory as well as the number of issued instructions carried by an issued instruction bus.

Reducing instruction transactions in a microprocessor

A data processing unit is described which comprises a central processing unit, a bus coupled with the central processing unit to access a device via address and data lines coupled with the bus. A debug unit is coupled to the bus, a protection unit is coupled with the bus and with the debug unit for protecting access on the bus. The protection unit is programmable to operate in a protecting mode in which the bus can be protected and in a debug mode in which a signal is sent to the debug unit, whereupon the debug unit generates a debug signal.

Data processing unit with debug capabilities using a memory protection unit

The present invention relates to a method of context switching from a first task to a second task in a data processing unit having a register file with a plurality of general purpose registers and a context switch register, a memory comprising a previous context save area and an unused context save area. The memory is coupled with the register file and an instruction control unit with a program counter register and a program status word register coupled with the memory and the register file. The method comprises the steps of acquiring a new save area from said unused save area, storing the context of the first task in said new area, linking the new area with said previous context save area.

Data processing unit with hardware assisted context switching capability

The data processing device according to the invention comprises an instruction providing unit having an input and an output, a pipeline unit for processing data having input and output stages, a loop pipeline unit for processing a loop instruction having input and output stages, said input stages of said pipeline units being coupled to said output of said instruction providing unit, said instruction providing unit providing data for said pipelines, and said pipeline units processing said data independently.

Growing community of inventors

San Jose, CA, United States of America

Eric John Chesters