Apple Inc.

Arm Limited

Eric Jason Furbish

Tyler J Huberty

Sandeep Kumar Gupta

Vivek Venkatraman

Stephen G Meier

Simon John Craske

Srinivasa Rangan Sridharan

Jonathan William Brawn

Stephan G Meier

Andrew J Beaumont-Smith

John D Pape

Brandon H Dwiel

Mridul Agarwal

Peter G Soderquist

Peter Logan Harrod

Chandan Shantharaj

Yanran Yang

Sahil Kapoor

An apparatus includes a cache memory circuit, a prefetcher circuit, and a prefetch deny list circuit, including a plurality of entries, may be included. The cache memory circuit may be configured to store information retrieved from a lower-level memory. The prefetcher circuit may be configured to generate a prefetch request for a particular prefetch address. The prefetch deny list circuit may be configured to allocate, in response to an indication from the cache memory circuit that a previously prefetched address went unused, a given entry, of the plurality of entries, for the previously prefetched address. The prefetch deny list circuit may be further configured to determine whether a particular address for a particular prefetch request corresponds to an active one of the plurality of entries. In response to a determination that a particular active entry corresponds to the particular address, prefetch deny list circuit may deny the particular prefetch request.

Deny list for a memory prefetcher circuit

A cache may store critical cache lines and non-critical cache lines, and may attempt to retain critical cache lines in the cache by, for example, favoring the critical cache lines in replacement data updates. Multiple levels of criticality may be available for a given cache line and cache circuitry may adjust the criticality value of in response to a criticality event. One or more upper criticality levels may be masked when selecting a victim cache line for replacement.

Criticality-informed caching policies with multiple criticality levels

A prefetcher for a coprocessor is disclosed. An apparatus includes a processor and a coprocessor that are configured to execute processor and coprocessor instructions, respectively. The processor and coprocessor instructions appear together in code sequences fetched by the processor, with the coprocessor instructions being provided to the coprocessor by the processor. The apparatus further includes a coprocessor prefetcher configured to monitor a code sequence fetched by the processor and, in response to identifying a presence of coprocessor instructions in the code sequence, capture the memory addresses, generated by the processor, of operand data for coprocessor instructions. The coprocessor is further configured to issue, for a cache memory accessible to the coprocessor, prefetches for data associated with the memory addresses prior to execution of the coprocessor instructions by the coprocessor.

Coprocessor prefetcher

A cache may store critical cache lines and non-critical cache lines, and may attempt to retain critical cache lines in the cache by, for example, favoring the critical cache lines in replacement data updates, retaining the critical cache lines with a certain probability when victim cache blocks are being selected, etc. Criticality values may be retained at various levels of the cache hierarchy. Additionally, accelerated eviction may be employed if the threads previously accessing the critical cache blocks are viewed as dead.

Mitigating retention of previously-critical cache lines

Criticality-informed caching policies

A list of program instructions are mapped into memory addresses to form an executable program by simulating their execution in turn so as to determine a memory address of a next program instruction to be executed. That memory address is then examined to determine if a program instruction has already been mapped thereto. If the memory address is empty, then the next program instruction from the list is mapped to that empty memory address and the execution of that next program instruction is simulated and the process repeated. If the memory address is not empty, then the program instruction read from that memory address is simulated again and the process repeated.

Forming an executable program from a list of program instructions

A test program for a data processing apparatus is produced using a genetic algorithm which mutates instances being ordered lists of program instructions within a population forming the test program. The populations are evaluated using a metric by which the population as a whole is scored for its stimulation of predetermined functional points within the data processing apparatus when a determination is being made as to whether or not a particular instance should be swapped in or out of the population.

Scoring mechanism for automatically generated test programs

Software built in self test computer programsare generated using a genetic algorithmtechnique. A fault simulatoris used to simulate candidate software built in self test computer programs and compare the simulated execution, such to deliberately introduced test faults, with expected execution outcomes previously derived for that candidate program to determine the sensitivity of that candidate program to the faults which are introduced. This score can be fed back into the genetic algorithm mutation to converge the mutation process upon appropriately fault sensitive software built in self test program code.

Generation of a computer program to test for correct operation of a data processing apparatus

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Austin, TX, United States of America

Eric Jason Furbish