Commissariat a L'energie Atomique

Commissariat a L'energie Atomique Et Aux Energies Alternatives

Centre National De La Recherche Scientifique

S.o.i.tec Silicon on Insulator Technologies

Commissariat À L'énergie Atomique Et Aux Énergies Alternatives

Université Grenoble Alpes

Université Joseph Fourier

S.o.i. Tec Silicon on Insulator Technologies, S.a.

Commissariat À L'energie Atomique (Cea)

Commissariat a L'atomique

Eric Jalaguier

Fabrice Letertre

Hubert Moriceau

Bernard Aspar

Christelle Charpin-Nicolle

Yves Mathieu Le Vaillant

Serge Blonkowski

Nicolas Guillaume

Michel Bruel

Julien Buckley

Jean-Charles Souriau

Gabriele Navarro

Xavier Chevalier

Norbert Moussy

Thierry Baron

Guy Feuillet

Ludovic Poupinet

Claude Jaussaud

Luca Perniola

François Marion

Stephane Pocas

Roland Madar

Gérard Bidan

Stéphane Pocas

Guy Royal

Boubacar Traore

Patrice Gonon

Guillaume Gay

Yves Mathieu Levaillant

This method comprises the following steps:

Method for manufacturing resistive memory cells

A filament type non-volatile memory device, includes a first electrode, a second electrode and an active layer extending between the first electrode and the second electrode, the active layer electrically interconnecting the first electrode to the second electrode, the device being suitable for having: a low resistive state, in which a conducting filament electrically interconnecting the first electrode to the second electrode uninterruptedly extends from end to end through the active layer, the filament having a low electric resistance, and a highly resistive state, in which the filament is broken, the filament having a high electric resistance. The device further includes a shunt resistance electrically connected in parallel to the active layer, between the first electrode and the second electrode.

Filamentary type non-volatile memory device

A memory device, containing a first electrode, a second electrode and an oxide layer arranged between the first electrode and the second electrode, is produced. The oxide layer has a first zone and a second zone, with the first zone surrounding or being located on either side of the second zone, with the minimum distance dseparating the two electrodes on the second zone of the oxide layer being less than the minimum distance dseparating the two electrodes on the first zone of the oxide layer.

Memory device

The invention relates to a method for functionalizing an electrically conductive substrate, which is not a substrate made of gold, via a layer of chemical compounds, said method comprising the following steps:

Method for functionalizing a solid substrate, other than a substrate made of gold, via specific chemical compounds

A process for obtaining an array of nanodots () for microelectronic devices, characterized in that it comprises the following steps:

Process for obtaining an array of nanodots

A method of making a non-volatile double-gate memory cell. The gate of the control transistor is formed with a relief of a semiconductor material on a substrate. The control gate of the memory transistor is formed with a sidewall of the relief of a semiconductor material configured to store electrical charge. A first layer is deposited so as to cover the stack of layers. The first layer is etched so as to form a first pattern juxtaposed on the relief. A second layer is formed on the first pattern. The second layer is etched so as to form on the first pattern a second pattern having a substantially plane upper face.

Method of making a non-volatile double gate memory cell

A process for manufacturing a stacked structure comprising at least one thin layer bonded to a target substrate, in which a thin layer is formed by introduction gaseous species into an initial substrate, to form a weakened layer separating a film from the rest of the initial substrate, a first contact face of the thin layer is bonded to a face of an intermediate substrate by molecular adhesion, and the initial substrate is fractured at the weakened layer so as to expose a free face of the thin layer. The intermediate substrate is then removed in order to obtain the stacked structure.

Manufacturing process for a stacked structure comprising a thin layer bonding to a target substrate

The invention relates to a process for manufacturing a stacked structure comprising at least one thin layer bonding to a target substrate, comprising the following steps:

An assembly method to enable local electrical bonds between zones located on a face of a first substrate and corresponding zones located on a face of a second substrate, the faces being located facing each other, at least one of the substrates having a surface topography. The method forms an intermediate layer including at least one burial layer on the face of the substrate or substrates having a surface topography to make it (them) compatible with molecular bonding of the faces of substrates to each other from a topographic point of view, resistivity and/or thickness of the intermediate layer being chosen to enable the local electrical bonds, brings the two faces into contact, the substrates positioned to create electrical bonds between areas on the first substrate and corresponding areas on the second substrate, and bonds the faces by molecular bonding.

Assembling two substrates by molecular adhesion

The invention relates to a DRAM memory device with a capacity associated with a field effect transistor, in which all or some of the molecules capable of storing the loads comprising a polyoxometallate are incorporated into the capacity, or a flash-type memory using at least one field effect transistor, in which the molecules capable of storing the loads comprising a polyoxometallate are incorporated into the floating grid of the transistor. The invention also relates to a method for producing on such device and to an electronic appliance comprising one such memory device.

Polyoxometallates in memory devices

A method of producing a substrate that has a transfer crystalline layer transferred from a donor wafer onto a support. The transfer layer can include one or more foreign species to modify its properties. In the preferred embodiment an atomic species is implanted into a zone of the donor wafer that is substantially free of foreign species to form an embrittlement or weakened zone below a bonding face thereof, with the weakened zone and the bonding face delimiting a transfer layer to be transferred. The donor wafer is preferably then bonded at the level of its bonding face to a support. Stresses are then preferably applied to produce a cleavage in the region of the weakened zone to obtain a substrate that includes the support and the transfer layer. Foreign species are preferably diffused into the thickness of the transfer layer prior to implantation or after cleavage to modify the properties of the transfer layer, preferably its electrical or optical properties. The preferred embodiment produces substrates with a thin InP layer rendered semi-insulating by iron diffusion.

Wafer and method of producing a substrate by transfer of a layer that includes foreign species

A method of producing a substrate that has a transfer crystalline layer transferred from a donor wafer onto a support. The transfer layer can include one or more foreign species to modify its properties. In the preferred embodiment an atomic species is implanted into a zone of the donor wafer that is substantially free of foreign species to form an embrittlement or weakened zone below a bonding face thereof, with the weakened zone and the bonding face delimiting a transfer layer to be transferred. The donor wafer is preferably then bonded at the level of its bonding face to a support. Stresses are then preferably applied to produce a cleavage in the region of the weakened zone to obtain a substrate that includes the support and the transfer layer. Foreign species are preferably diffused into the thickness of the transfer layer prior to implanbumtation or after cleavage to modify the properties of the transfer layer, preferably its electrical or optical properties. The preferred embodiment produces substrates with a thin InP layer rendered semi-insulating by iron diffusion.

Given a component comprising at least one active area formed on a substrate and designed to be coupled to a light guide, a support is used, at least one hole is formed in the support starting from one face of this support, this hole being designed to receive one end of the guide, the substrate is fixed to the other face of the support by forming the hole facing the active area if the active area has already been formed, and otherwise it is formed on the substrate facing the hole and the end of the guide is placed in the hole. The optical system is obtained by optically coupling two devices thus obtained.

Method and device for passive alignment of optical waveguides and optoelectronic components and optical system using said device

The invention relates to a process for manufacturing a stacked structure comprising at least one thin layer bonding to a target substrate, comprising the following steps: a) formation of a thin layer starting from an initial substrate, the thin layer having a free face called the first contact face, b) putting the first contact face into bonding contact with a face of an intermediate support, the structure obtained being compatible with later thinning of the initial substrate, c) thinning of the said initial substrate to expose a free face of the thin layer called the second contact face and opposite the first contact face, d) puffing a face of the target substrate into bonding contact with at least part of the second contact face, the structure obtained being compatible with later removal of all or some of the intermediate support, e) removal of at least part of the intermediate support in order to obtain the said stacked structure.

Growing community of inventors

Saint Martin d'Uriage, France

Eric Jalaguier