Texas Instruments Corporation

University of Houston System

Eric J Stotzer

Elana D Granston

Joseph R Zbiciak

Todd T Hahn

Michael D Asal

Richard H Scales

Alan S Ward

Gary L Swoboda

Alan Davis

David J Hoyle

Natarajan Kurian Seshan

Reid E Tatge

Ji Chen

George Zouridakis

Dineel Diwakar Sule

Gayathri Krishnamurthy

Xiaojing Yuan

Yanmin Wu

A method of register allocation in complier using a computer instruction set having tiered instructions that accesses differing numbers of registers makes a first preliminary register allocation attempt using an initially specified register set for each instruction. If this fails, the method identifies instructions having an initially specified limited register having a variable not register allocatable. The method makes a second preliminary register allocation attempt except using a less restrictive register set for the identified instructions. This method employs a next less restrictive register set and re-attempts preliminary register allocations for instructions with more than two levels of register restriction.

Tiered register allocation

The present invention provides devices for screening the skin of an individual in real time using a region-fusion based segmentation with narrow band graph partitioning algorithm to analyze and classify a region of interest of the skin as benign or malignant. Also, provided is a method for screening the skin of an individual using the devices described herein. In addition the present invention provides a digital processor-implemented system for classifying a region of interest on the skin and a processor readable medium having processor-executable instructions to perform skin cancer detection.

Device and software for screening the skin

This invention is useful in a very long instruction word data processor that fetches a predetermined plural number of instructions each operation cycle. A predetermined one of these instructions is used as a special header. This special header has a unique encoding different from any normal instruction. When decoded this special header instructs decode hardware to decode this fetch packet in a special way. In one embodiment a bit field in the header signals the decode hardware whether to decode each instruction word normally or in an alternative way. The header may include extension opcode bits corresponding to each of the other instruction slots. In another embodiment another bit field signals whether to decode an instruction field as one normal length instruction or as two half-length instructions.

VLIW optional fetch packet header extends instruction set space

This invention employs a 16-bit instruction set that has a subset of the functionality of the 32-bit instruction set. In this invention 16-bit instructions and 32-bit instructions can coexist in the same fetch packet. In the prior architecture 32-bit instructions may not span a 32-bit boundary. The 16-bit instruction set is implemented with a special fetch packet header that signals whether the fetch packet includes some 16-bit instructions. This fetch packet header also has special bits that tell the hardware how to interpret a particular 16-bit instruction. These bits essentially allow overlays on the whole or part of the 16-bit instruction space. This makes the opcode space larger permitting more instructions than with a pure 16-bit opcode space.

Software source transfer selects instruction word sizes

The present invention provides methods specifically geared to finding natural splits in wide, nearly symmetric dependence graphs and assigning the components of the split to clusters in a VLIW processor. The basic approach of these methods is to assign a node n of the dependence graph to the cluster to which it has the strongest affinity. A node n has the strongest affinity to the cluster containing its closest common ancestor node. Then, the mirror image node or nodes of the node n are located if they are present in the graph and are assigned to other clusters in the processor to which they have the strongest affinity.

Partitioning symmetric nodes efficiently in a split register file architecture

A method for software pipelining of irregular conditional control loops including pre-processing the loops so they can be safely software pipelined. The pre-processing step ensures that each original instruction in the loop body can be over-executed as many times as necessary. During the pre-processing stage, each instruction in the loop body is processing in turn (N). If the instruction can be safely speculatively executed, it is left alone (N). If it could be safely speculatively executed except that it modifies registers that are live out of the loop, then the instruction can be pre-processed using predication or register copying (N, N, N). Otherwise, predication must be applied (N). Predication is the process of guarding an instruction. When the guard condition is true, the instruction executes as though it were unguarded. When the guard condition is false, the instruction is nullified.

Method for software pipelining of irregular conditional control loops

A data processing system with a microprocessor that has an instruction execution pipeline that includes fetch and decode stages and several functional execution units. Fetch packets contain a plurality of instruction words. Execution packets include a plurality of instruction words that can be executed in parallel by two or more execution units. An execution packet can span two or more fetch packets. An add (k) constant to program counter (ADDKPC) instruction is provided, such that a parameter specified by the ADDKPC instruction is combined with a value provided by a program counter of microprocessor. The ADDKPC instruction can also specify a number of delay slots after a branch instruction to be filled with virtual NOP instructions such that memory is not wasted with useless NOP instructions. An ADDKPC instruction can provide a relative address for use as a return address. A plurality of predicated ADDKPC instructions can provide a return address selected from a plurality of return addresses. A compiler can reorder code with an ADDKPC instruction to absorb useless NOP instructions.

Microprocessor with an instruction immediately next to a branch instruction for adding a constant to a program counter

A method for reducing total code size in a processor having an exposed pipeline may include the steps of determining a latency between a load instruction, and a using instruction and inserting a NOP field into the defining or using instruction. When inserted into the load instruction, the NOP field defines the following latency following the load instruction. When inserted into the using instruction, the NOP field defines the latency preceding the using instruction. In addition, a method for reducing total code size during branching may include the steps of determining a latency following a branch instruction for initiating a branch from a first point to a second point in an instruction stream, and inserting a NOP field into the branch instruction. Further, a method according to this invention may include the steps of locating delayed effect instructions followed by NOPs, such as load or branch instructions, within a code; deleting the NOPs from the code; and inserting a NOP field into the delayed effect instructions. Apparatus according to this invention may include a processor including a code containing a delayed effect instruction, wherein the delayed effect instruction includes a NOP field.

Methods and apparatus for reducing the size of code with an exposed pipeline by encoding NOP operations as instruction operands

A method for reducing a code size of a software pipelined loop, the software pipelined loop having a kernel and an epilog. The method includes first evaluating a stage of the epilog. This includes selecting a stage of the epilog to evaluate ( ) and evaluating an instruction in a reference stage. This includes identifying an instruction in the reference stage that is not present in the selected stage of the epilog ( ) and determining if the identified instruction can be speculated ( ). If the identified instruction can be speculated, such is noted. If the instruction cannot be speculated, it is determined whether the identified instruction can be predicated ( ). If the instruction can be predicated, it is marked as needing predication ( ). Next, it is determined if another instruction in the reference stage is not present in the selected stage of the epilog ( ). If there is, the instruction evaluation is repeated. If there is another stage of the epilog to evaluate, the evaluation is repeated ( ).

Method for collapsing the prolog and epilog of software pipelined loops

A method for implementing a variable length delay instruction includes the steps of designating a source register for holding information and designating a destination register for retrieving the information. A first number of cycles before retrieval of the information to the destination register then is determined, and the information is transferred from the source register to delaying device, such as queuing device, for the first number of cycles. Finally, the information is written from the delaying device to the destination register. An apparatus for implementing variable length delay instructions includes an input line for reading information from a source register; delaying device for receiving said information read from the source register; a multiplexer; and a select line. A trigger signal is transmitted to the multiplexer, thereby instructing the multiplexer to write the information to a destination register.

System and method of implementing variabe length delay instructions, which prevents overlapping lifetime information or values in efficient way

A method of operating a multiple execution unit microprocessor in a software pipelined loop is disclosed. This method allows the microprocessor to respond to interrupt requests and other runtime conditions during execution of a software pipelined loop utilizing multiple assignment of registers. In one embodiment, the method comprises branching out of the software pipelined loop, upon occurrence of an interrupt request, to an interrupt epilog that consumes in-flight register values and sets the interrupt return pointer to the address of an interrupt prolog. The interrupt is then taken. The interrupt prolog is a subset of the loop prolog, and restores the processor to an operational state equivalent to one that would have existed had the interrupt not been taken. Loop execution is then resumed without data loss or corruption.

Interruptable multiple execution unit processing during operations utilizing multiple assignment of registers

A method for testing a digital processor 11 in which a test port 1149 is used to transfer trace data from the digital processor to a test host processor 1101 under control of a user definable program which executes in response to predetermined events on the digital processor. Trace data is gathered while an application program loaded in program memory 61 is executed by the digital processor. Trace data is temporarily stored in a trace region 99 of data memory 25 by user definable code which is executed in a background manner by the digital processor in response to trigger events. The trigger events are also enabled by user definable code which enables various portions of analysis hardware 1217. Trace data is transferred from the digital processor to the test host processor through test port 1149 by sending a notification signal to the test host processor by means of message passing register 1216. The digital processor then monitors the message passing register for a handshake signal from the test host processor. When a handshake signal is received, trace data is written into the message passing register by user definable code in a background manner and transferred to the test host processor.

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Houston, TX, United States of America

Eric J Stotzer