International Business Machines Corporation

Eric J Stec

Jeremy Alan Arnold

Scott Alan Moore

Gregory Allan Olson

Christopher James Kundinger

Nicholas D Lindberg

In an embodiment, an indicator is set to indicate that all of a plurality of most significant bytes of characters in a character array are zero. A first index and an input character are received. The input character comprises a first most significant byte and a first least significant byte. The first most significant byte is stored at a first storage location and the first least significant byte is stored at a second storage location, wherein the first storage location and the second storage location have non-contiguous addresses. If the first most significant byte does not equal zero, the indicator is set to indicate that at least one of a plurality of most significant bytes of the characters in the character array is non-zero. The character array comprises the first most significant byte and the first least significant byte.

Storing the most significant and the least significant bytes of characters at non-contiguous addresses

A method, apparatus, and program product are provided for managing power consumption in a computer system based on the degree with which performance of tasks can be degraded in order to save power. A criticality value controls the degree with which performance of a task may be degraded is associated with tasks within a computer system. Power consumption of the computer system is then managed based on the criticality values associated with tasks executing within the computer system. A reduction in computer system power consumption can be realized by degrading the performance of non-critical tasks, which is accomplished by reducing the power consumed by at least a portion of the computer system. Power can also be reduced by scheduling non-critical tasks to portions of the computer system and reducing power consumption of other portions of the computer system.

Reducing power consumption of components based on criticality of running tasks independent of scheduling priority in multitask computer

A method and circuit for eliminating silent store invalidation propagation in shared memory cache coherency protocols, and a design structure on which the subject circuit resides are provided. A received data value is compared with a stored cache data value. When the received data value matches the stored cache data value, a first squash signal is generated. A received write address is compared with a reservation address. When the received write address matches the reservation address, a reservation signal is generated and inverted. The first squash signal and the inverted reservation signal are combined to selectively produce a silent store squash signal. The silent store squash signal cancels sending an invalidation signal.

Eliminating silent store invalidation propagation in shared memory cache coherency protocols

Methods, systems and computer program products for CPU signaturing to aide in performance analysis. Exemplary embodiments include a performance analysis method including identifying a workload having one or more testcases, assigning a CPU signature to each of the one or more testcases, calling a CPU signature application programming interface that toggles the CPU to generate the CPU signature, passing four parameters to the CPU signature application programming interface, prior to running each of the one or more testcases of the workload, generating the CPU signature, dynamically determining a run order of the one or more testcases at a run time of the workload and reviewing performance data during the running of each of the one or more testcases, each of the one or more testcases being identifiable by its respective CPU signature.

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Rochester, MN, United States of America

Eric J Stec