Micron Technology Incorporated

Nan Ya Technology Corporation

Eric J Stave

Timothy Mowry Hollis

Thomas H Kinsley

Gary L Howe

Matthew Alan Prather

Yogesh Sharma

James S Rehmeyer

Miles S Wiscombe

Chan H Yoo

Gregory A King

Randon K Richards

Phillip G Wald

George Edward Pax

Baekkyu Choi

George E Pax

Dean D Gans

Jeffrey P Wright

Tyler J Gomm

Kang-Yong Kim

Joseph Thomas Pawlowski

Brian W Huber

Matthew B Leslie

Markus H Geiger

Dirgha Khatri

Elancheren Durai

Scott Richard Cyr

Daniel Benjamin Stewart

Quincy R Holton

Todd M Buerkle

Ron A Hughes

Anthony D Newton

Boe L Holbrook

Methods, apparatuses, and systems related to voltage management of memory apparatuses/systems are described. The memory device can include circuitry configured to determine an operating frequency of a clock signal for an ongoing or an upcoming memory operation. The memory device may generate a control indicator for increasing a system voltage for higher operating frequencies, for decreasing the system voltage for lower operating frequencies, or a combination thereof.

Apparatus with data-rate-based voltage control mechanism and methods for operating the same

Methods, systems, and devices for power management for a memory device are described. For example, a memory device may include one or more memory dies and may be configured to operate using a first supply voltage and a second supply voltage. The first supply voltage may be associated with a first defined voltage range, and the second supply voltage may be associated with a second defined voltage range. The memory device may include a power management integrated circuit (PMIC) that is coupled with the one or more memory dies and provides the supply voltages to the one or more memory dies. The PMIC may be configured to provide, to the one or more memory dies, a first voltage that is within the first defined voltage range as the first supply voltage and a second voltage that is outside the second defined voltage range as the second supply voltage.

Power management for a memory device

Systems, apparatuses, and methods for operating a memory device or devices are described. A memory device or module may introduce latency in commands to coordinate operations at the device or to improve timing or power consumption at the device. For example, a host may issue a command to a memory module, and a component or feature of the memory module may receive the command and modify the command or the timing of its execution in manner that is invisible or non-disruptive to the host while facilitating operations at the memory module. In some examples, components or features of a memory module may be disabled to effect or introduce latency in operation without affecting timing or operation of a host device. A memory module may operate in different modes that allow for different latencies; the use or introduction of latencies may not affect other features or operability of the memory module.

Methods for memory power management and memory devices and systems employing the same

A device includes a clock input circuit that when in operation receives a clock signal and transmits an internal clock signal based on the clock signal. The device also includes an internal clock generator coupled to the clock input circuit to receive the internal clock signal, wherein the internal clock generator comprises clock adjustment circuitry that when in operation generates a phase controlled internal clock signal having subsequent clock edges based upon a single clock edge of the internal clock signal, wherein the phase controlled internal clock signal comprises a first frequency as a multiple of a second frequency of the internal clock signal.

Systems and techniques for jitter reduction

Systems, apparatuses, and methods for test devices having parallel impedances to reduce measurement input impedance are disclosed. An apparatus includes a test input terminal, a measurement output terminal, a reference voltage potential node, and a parallel resistor. The test input terminal is configured to electrically connect to a signal output terminal of a signal generator. The test input terminal is configured to receive a test signal from the signal generator via the signal output terminal. The measurement output terminal electrically connects to a measurement input terminal of an electrical measurement instrument. The parallel resistor is electrically connected from the measurement output terminal to the reference voltage potential node. A system includes the apparatus and the electrical measurement instrument. A method includes providing a test signal to the test device, verifying the test signal using the electrical measurement instrument, and providing the test signal to a device under test.

Test devices having parallel impedances to reduce measurement input impedance and related apparatuses, systems, and methods

Methods, systems, and devices for on-die termination configuration for a memory device are described. In some examples, a memory device may determine a connection option from a set of connections options for which an ODT pin of the memory device is configured. Each connection option may correspond to a termination configuration for a different pin, such as a command and address (CA) pin, a clock (CK) pin, or a chip select (CS). Based on the determined connection option, the memory device may identify a respective termination option for each of the different pins, such as a first termination option for the CA pin, a second termination option for the CK pin, and a third termination option for the CS pin, and configure each of the different pins according to the respective termination option for that pin.

On-die termination configuration for a memory device

Memory devices, systems including memory devices, and methods of operating memory devices are described, in which clock trees can be separately optimized to provide a coarse alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal), and/or in which individual memory devices can be isolated for fine-tuning of device-specific alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal). Moreover, individual memory devices can be isolated for fine-tuning of device-specific equalization of a command/address signal (and/or a chip select signal or other control signal).

Methods for tuning command/address bus timing and memory devices and memory systems using the same

A method of operating an oscilloscope is disclosed. The method comprises providing a bit stream comprising pseudo-random data to an oscilloscope across a data path characterized by sufficient signal degradation to prevent the oscilloscope from reliably triggering a sweep of an eye pattern based on receiving the pseudo-random data; inserting a predetermined sequence of bits into the bit stream at predetermined periodic intervals to open the eye pattern sufficiently during each of the periodic intervals to permit the oscilloscope to trigger the sweep of the eye pattern; and generating the eye pattern based at least in part on the pseudo-random data and excluding the predetermined sequence of bits from the sweep of the eye pattern. Oscilloscopes configured to trigger according to a predetermined system of bits at predetermined intervals are also disclosed.

Methods for triggering oscilloscopes and oscilloscopes employing the same

An apparatus is provided, comprising a plurality of memory devices and a buffering device that permits memory devices with a variety of physical dimensions and memory formats to be used in an industry-standard memory module format. The buffering device includes memory interface circuitry and at least one first-in first-out (FIFO) or multiplexer circuit. The apparatus further comprises a parallel bus connecting the buffering device to the plurality of memory devices. The parallel bus includes a plurality of independent control lines, each coupling the memory interface circuitry to a corresponding subset of a plurality of first subsets of the plurality of memory devices. The parallel bus further includes a plurality of independent data channels, each coupling the at least one FIFO circuit or multiplexer circuit to a corresponding subset of a plurality of second subsets of the plurality of memory devices.

Memory devices, modules and systems having memory devices with varying physical dimensions, memory formats, and operational capabilities

Apparatuses for characterizing system channels and associated methods and systems are disclosed. In one embodiment, a tester is coupled to an adaptor configured to plug into a CPU socket of a system platform (e.g., a motherboard). The motherboard includes a memory socket that is connected to the CPU socket through system channels. The adaptor may include a connector configured to physically and electrically engage with the CPU socket, an interface configured to receive test signals from the tester, and circuitry configured to internally route the test signals to the connector. The adaptor, if plugged into the CPU socket, can facilitate the tester to directly assess signal transfer characteristics of the system channels. Accordingly, the tester can determine optimum operating parameters for the memory device in view of the system channel characteristics.

Apparatuses for characterizing system channels and associated methods and systems

Methods, systems, and apparatuses related to memory operation with on-die termination (ODT) are provided. A memory device may be configured to provide ODT at a first portion (e.g., rank) during communications at a second portion (e.g., rank). For example, a memory device may receive a first command instructing a first portion to perform a first communication. The device may transmit, from the first portion, a signal instructing a second portion to enter an ODT mode. The device may perform, with the first portion, the first communication with a host while the second portion is in the ODT mode. The signal may be provided at an ODT I/O terminal of the first portion coupled to an ODT I/O terminal of the second portion.

Methods for on-die memory termination and memory devices and systems employing the same

Methods, systems, and devices for voltage adjustment based on, for example, pending refresh operations are described. A memory device may periodically perform refresh operations to refresh volatile memory cells and may at times postpone performing one or more refresh operations. A memory device may determine a quantity of pending (e.g., postponed) refresh operations, such as by determining a quantity of refresh intervals that have elapsed without receiving or executing a refresh command, among other methods. A memory device may pre-emptively adjust (or cause to be adjusted) a supply voltage associated with the memory device or memory device component based on the quantity of pending refresh operations to prepare for the current demand associated with the performing the one or more pending refresh operations. For example, the memory device may increase a supply voltage associated with one or more components to prepare for performing multiple pending refresh operations.

Voltage adjustment based on pending refresh operations

Methods, systems, and apparatuses related to memory operation with on-die termination (ODT) are provided. A memory device may be configured to provide ODT at a first portion (e.g., rank) during multiple communications at a second portion (e.g., rank). For example, a memory device may receive a first command instructing a first portion to perform a first communication and instructing a second portion to enter an ODT mode. The device may perform, with the first portion, the first communication with a host while the second portion is in the ODT mode. The device may receive a second command instructing the first portion to perform a second communication, and the device may perform, with the first portion, the second communication while the second portion remains in the ODT mode. The second portion may persist in the ODT mode for an indicated number of communications, or until instructed to exit the ODT mode.

Growing community of inventors

Meridian, ID, United States of America

Eric J Stave