Micron Technology Incorporated

Eric J Smith

Michael D Chaine

James E Davis

Milind Nemchand Furia

Salman Akram

Brent Keeth

Troy A Manning

Todd A Merritt

Brian L Johnson

Shubneesh Batra

Chris G Martin

Joseph C Sher

Michael V Ho

An apparatus includes a protection circuit electrically connected to first and second voltage domains. The protection circuit includes a first silicon-controlled rectifier (SCR) and a second SCR connected in anti-parallel configuration. The first SCR is configured to connect the first voltage domain and the second voltage domain based on detection of a first triggering condition. The second SCR is configured to connect the second voltage domain and the first voltage domain based on detection of a second triggering condition. The protection circuit is configured to isolate the first and second voltage domains without the triggering conditions.

Apparatus with voltage protection mechanism

Semiconductor devices having busing layouts configured to reduce on-die capacitance are disclosed herein. In one embodiment, a semiconductor device includes an electrostatic discharge device electrically connected in parallel with an integrated circuit and configured to divert high voltages generated during an electrostatic discharge event away from the integrated circuit. The semiconductor device further includes a signal bus and a power bus electrically connected to the electrostatic discharge device. The signal bus includes a plurality of first fingers grouped into first groups and the power bus includes a plurality of second fingers grouped into second groups. The first groups are positioned generally parallel to and interleaved between the second groups.

Semiconductor devices having electrostatic discharge layouts for reduced capacitance

A method of reducing parasitic capacitance in an integrated circuit having three or more metal levels is described. The method comprises forming a bond pad at least partially exposed at the top surface of the integrated circuit, forming a metal pad on the metal level below the bond pad and forming an underlying metal pad on each of the one or more lower metal levels. In the illustrated embodiments, the ratio of an area of at least one of the underlying metal pads to the area of the bond pad is less than 30%. Parasitic capacitance is thus greatly reduced and signal propagation speeds improved.

Method and structures for reduced parasitic capacitance in integrated circuit metallizations

A programming circuit for an anti-fuse utilizes a boot circuit that charges a capacitor to the supply voltage during a non-programming period. Anti-fuse is to be programmed, the plate of the capacitor to which the supply voltage has been applied is switched to 0 volts, thereby causing the other plate of the capacitor to output a negative voltage. This negative voltage is switched to one plate of an anti-fuse, and the other plate of the anti-fuse receives a positive voltage from an external source. A voltage is thereby applied across the anti-fuse that is greater than any voltage applied to any node of the integrated circuit.

Method and apparatus for programming anti-fuses using internally

A programming circuit programs an anti-fuse having first and second terminals with the programming circuit and the anti-fuse being fabricated in the same integrated circuit. The programming circuit includes a first external terminal of the integrated circuit coupled to the first terminal of the anti-fuse. The first external terminal is adapted to receive a first programming voltage having a predetermined polarity. A second external terminal of the integrated circuit is adapted to receive a second programming voltage having a polarity opposite that of the first programming voltage. A voltage translation circuit is coupled between the second external terminal and the second terminal of the anti-fuse and includes an enable terminal adapted to receive an enable signal. The voltage translation circuit is operable to couple the second programming voltage to the second terminal of the anti-fuse in response to the enable signal being active. When the enable signal is inactive, the voltage translation circuit isolates both positive and negative voltages on the second external terminal from the second terminal of the anti-fuse.

Growing community of inventors

Boise, ID, United States of America

Eric J Smith