Micron Technology Incorporated

Eric J Rich-Plotkin

Christopher Gordon Wieduwilt

Jiyun Li

Dennis G Montierth

Boon Hor Lam

Shawn M Hilde

Greg S Hendrix

An exemplary memory includes a memory cell array configured to store a plurality of data bits each associated with a respective column plane, and an input/output circuit including a compression circuit configured to provide error data based on a comparison between a bit of the plurality of data bits received from the memory cell array and an expected value and based on a respective column plane of the memory cell array with which the bit is associated. The compression circuit is further configured to encode a column plane error code based on the error data for provision to a data terminal.

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Boise, ID, United States of America

Eric J Rich-Plotkin