Intel Corporation

Eric J M Moret

Pooya Tadayon

Nikos Kaburlasos

David Shia

Tarek A Ibrahim

Paul J Diglio

Michael L Rutigliano

Phani Kumar Kandula

David N Lombard

Karumbu Meyyappan

Srinivas Venkata Ramanuja Pietambaram

Mark J Luckeroth

Marc Beuchat

John Kelbert

Brad Bittel

Rodrigo De Oliveira Vivi

An electronic device comprises an electro-optical circuit package including at least photonic integrated circuit (PIC) having at least one light source and a package substrate; a printed circuit (PCB) including at least one optical connector to receive light from the at least one light source; and multiple liquid metal electrical contacts disposed between the package substrate and the PCB.

Reworkable zero-force insertion electrical optical package socket and method

In an optical circuit, a substrate can define a cavity that extends into a substrate front surface. A sidewall of the cavity can include a substrate optical port. An optical path can extend through the substrate from a connector optical port to the substrate optical port. A photonic integrated circuit (PIC) can attach to the substrate. A PIC front surface can include a plurality of electrical connections. A PIC edge surface can extend around at least a portion of a perimeter of the PIC between the PIC front surface and a PIC back surface. A PIC optical port can be disposed on the PIC edge surface and can accept or emit an optical beam along a PIC optical axis. The PIC optical axis can be aligned with the substrate optical port when the PIC is attached to the substrate.

Optical circuit with optical port in sidewall

Disclosed herein are embodiments of systems and methods for stable and elevated idle-mode temperature for assembled semiconductor devices. In an embodiment, a processor includes a communication interface configured to receive, from a first hardware component, instructions assigned to the processor for execution. The processor also includes temperature-measurement circuitry configured to monitor an on-chip temperature of the processor. The processor also includes control logic configured to: determine whether the processor is active or idle; determine whether the on-chip temperature of the processor exceeds a first threshold; based on determining that the processor is idle and that the on-chip temperature of the processor exceeds the first threshold, disable one or more idle-mode power-saving features of the processor; and selectively adjust one or more operating parameters of the processor to keep the on-chip temperature of the processor between the first threshold and a second (higher) threshold.

Systems and methods for stable and elevated idle-mode temperature for assembled semiconductor devices

Embodiments of the present disclosure describe wafer-level die testing devices having a base with a planar X-Y surface, a plurality of thermal actuators situated on the surface, wherein one or more of the plurality of thermal actuators is movable in relation to the base in at least one of the X or the Y directions, and one or more adjustable links, wherein each adjustable link is to adjust a relative position between an individual thermal actuator of the plurality of thermal actuators and one or more other thermal actuators of the plurality of thermal actuators in one or more of the X or the Y directions. Other embodiments may be described and/or claimed.

Adaptive thermal actuator array for wafer-level applications

In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing fast throughput die handling for synchronous multi-die testing. For instance, there is disclosed in accordance with one embodiment a device handler for testing functional silicon devices, the device handler including: a plurality of test interface units to electrically interface to the functional silicon devices for test; a plurality of thermal actuators, each being individually movable upon at least three axes; an optical alignment unit with a plurality of pick and place head pairs, in which the optical alignment unit is to move upon a horizontal plane and is to move between the plurality of test interface units and the plurality of thermal actuators; an upward facing camera to move with the optical alignment unit, the upward facing camera to optically locate a position of the plurality of test interface units; a plurality of downward facing cameras, each to optically locate a position of one of the plurality of functional silicon devices to be tested upon one of the plurality of thermal actuators; in which the device handler is to move the optical alignment unit out from between the plurality of test interface units and the plurality of thermal actuators; and in which the device handler is to align test probes affixed to the test interface units with the plurality of functional silicon devices to be tested and electrically interface the test probes with the functional silicon devices for testing. Other related embodiments are disclosed.

Systems, methods, and apparatuses for implementing fast throughput die handling for synchronous multi-die testing

Devices and methods useful for testing bare and packaged semiconductor dice are provided. As integrated circuit chips become smaller and increasingly complex, the interface presented by a chip for connectivity with power supplies and other components of the system into which it is integrated similarly becomes smaller and more complex. Embodiments of the invention provide micron-scale accuracy alignment capabilities for fine pitch device first level interconnect areas. Embodiments of the invention employ air-bearings to effectuate the movement and alignment of a device under test with a testing interface. Additionally, testing interfaces comprising membranes supported by thermal fluids are provided.

Positioning and socketing for semiconductor dice

In some embodiments, a temporary package for at-speed functional test of semiconductor chip, including high power chips, is presented. In this regard, a method is introduced including placing an integrated circuit die on a contactor layer, the contactor layer to electrically couple contacts on the integrated circuit die with contacts on a multi-layer substrate designed to be permanently attached with the integrated circuit die, placing an integrated heat spreader over the integrated circuit die, and bonding the integrated heat spreader with the substrate, the integrated heat spreader holding the integrated circuit die in place to form a temporary package. Other embodiments are also disclosed and claimed.

Growing community of inventors

Beaverton, OR, United States of America

Eric J M Moret