Intel Corporation

Marvell International Limited

Eric J Hoffman

Lawrence T Clark

Mark A Beiley

Tuan X Do

Raphael A Soetan

Vikas R Amrelia

Edward John Bawolek

Bart R McDaniel

Neil F Deutscher

Pradeep Elamanchili

Susan M Graham

Dale J Brown

An integrated circuit biases the substrate and well using voltages other than those used for power and ground. Tap cells inside the standard cell circuits are removed. New tap cells used to bias the substrate and well reside outside the standard cell circuits. The location of the new voltage power rails is designated prior to placement of the tap cells in the integrated circuit. The tap cells are then strategically placed near the power rails such that metal connections are minimized. Circuit density is thus not adversely impacted by the addition of the new power rails. Transistors are also placed inside the tap cells to address electrostatic discharge issues during fabrication.

Tap connections for circuits with leakage suppression capability

Briefly, in accordance with one embodiment of the invention, an integrated circuit has a voltage regulator that is used to provide a power supply potential to a memory circuit while a logic circuit is decoupled from a power supply potential.

Apparatus having a first circuit supplying a power potential to a second circuit under a first operating mode otherwise decoupling the power potential

Briefly, in accordance with one embodiment of the invention, a flip-flop operates as a master-slave flip flop in a test mode and operates as a pulsed latch in normal operation. Two clock signals having non-overlapping transitions are used to provide and control the flow of input data.

Flip-flop having multiple clock sources and method therefore

In a pixel having an electronic shutter, a method of increasing the retention time of the electronic shutter is disclosed. A reset signal is employed to drive a diode node to a predetermined voltage immediately after integration is completed. A sample signal is employed to control a pass gate. The sample signal includes a state where the sample signal is a negative voltage.

Method and apparatus for increasing retention time in image sensors having an electronic shutter

A voltage level shifter for changing digital bit levels between devices having different voltage levels. In addition to changing the voltage levels in the normal mode, the device includes additional transistors which are activated when the system is in a drowsy mode so as to cut DC current drain and to latch outputs to ignore extraneous inputs.

Voltage level shifter having zero DC current and state retention in drowsy mode

An architecture for self-calibration and fixed-pattern noise removal in imager chips. The column-to-column fixed pattern noise and/or pixel-to-pixel fixed pattern noise is determined through a self-calibration operation. During operation of the imager chip, when a value of a pixel is read, the read value is compensated with the fixed-pattern noise corresponding to either the column fixed pattern noise corresponding to the column having the pixel from which the value was read or to the pixel fixed pattern noise corresponding to the pixel from which the value was read.

Method and apparatus for self-calibration and fixed-pattern noise removal in imager integrated circuits

An apparatus comprising a charge pump configured to receive an input signal and to output incrementally a fixed amount of voltage for every selected edge of the input signal, an analog buffer coupled to said charge pump, the analog buffer feeding back a second voltage to said charge pump, the output of the charge pump linearly increases as a function of the fixed amount of voltage. A low power ramp generator that is created thereby may be used in analog to digital converters which are employed in devices such as imaging systems.

Low power ramp generator for use in single slope A/D

A method for providing an improved active pixel sensor cell having a soft-saturation circuit. The method includes providing a pixel node and a photodiode coupled to the pixel node. The photodiode receives light and converts the light into an electrical signal representative of light. A soft-saturation circuit for selectively affecting the electrical signal at the pixel node based on the electrical signal at the pixel node based on the electrical signal at the pixel node is also provided.

Sensor cell having a soft saturation circuit

CMOS pixel sensors have been of interest as replacements for CCD's in imaging applications. Such devices promise lower power and simpler system level design through fewer power supply voltages and higher functional integration. It is difficult and cost ineffective to utilize images to test active pixel sensors. Here, a method and apparatus for electrical testing of CMOS pixel sensors is described which involves electrically writing a pattern into the CMOS pixel sensors for the detection of adjacent cell shorts or stuck at faults as well as verification of read-channel circuit functionality and performance. The invention provides for an electrical testing of CMOS pixel array that is simple, time efficient and cost effective for use in, for example, production.

Method and apparatus for electrical test of CMOS pixel sensor arrays

A random number generator using, for example, a voltage controlled oscillator (VCO) which receives a noise input and at least one differential oscillator. The differential oscillator(s) provided oscillator signals to a differential sense amplifier which is sampled under control of the VCO.

Random number generator

An image sensor having a well-to-substrate diode as the photodetector. In a preferred embodiment, a modern salicided (CMOS) process is utilized to manufacture the image sensor. The field oxide region above the diode junction is transparent to visible light, thus allowing the photodiode competitive quantum efficiency as compared to devices having source/drain diffusion-to-substrate photodiodes fabricated on a non-salicided process. The photodiode can be integrated as part of a sensor array with digital circuitry using a relatively unmodified digital CMOS process. Furthermore, the structure allows the optical properties of the photodiode to be engineered by modifying the well without deleterious effects, to approximate a first order, on the characteristics of a FET built in another identical well.

Well to substrate photodiode for use in a CMOS sensor on a salicide

A circuit that includes at least two driver circuits. Each driver circuit receives analog information and drives a value related to the analog information to an analog bus. Each driver circuit also includes a select transistor to pass the value related to the analog information to the analog bus when the driver circuit is selected. The select transistor includes a source and a bulk. Each driver circuit further includes a bulk potential control circuit (BPCC) to couple the bulk to the source when the driver circuit is selected and to couple the bulk to a voltage supply when the driver circuit is not selected.

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Chandler, AZ, United States of America

Eric J Hoffman