Intel Corporation

Eric J Hoekstra

Abhishek R Appu

Prasoonkumar Surti

Joydeep Ray

Altug Koker

Balaji Vembu

Subramaniam M Maiyuran

Travis T Schluessler

Kamal Sinha

Kiran Chand Veernapu

Linda L Hurd

Wenyin Fu

Jonathan Kennedy

Bhushan M Borole

Vasanth Ranganathan

Murali Ramadoss

Guei-Yuan Lueh

Ankur N Shah

Nikos Kaburlasos

Elmoustapha Ould-Ahmed-Vall

Karthik Vaidyanathan

Adam T Lake

David M Puffer

John H Feit

Gabor Liktor

Aravindh V Anantaraman

Jeffery S Boles

Devan Burke

Abhishek Venkatesh

James A Valerio

Pattabhiraman K

Supratim Pal

Saurabh Sharma

Arthur Hunter, Jr

Slawomir Grajewski

Sanjeev S Jahagirdar

Eric J Asperheim

Subhajit Dasgupta

Daren J Schmidt

Srivallaba Mysore

Hiroshi Akiba

Saikat Mandal

Kalyan Kumar Bhiravabhatla

Jeffrey S Boles

Methods, systems and apparatuses may provide for technology that identifies that a first thread group of a pixel location is associated with a first shading rate, identifies that a second thread group of the pixel location is associated with a second shading rate, wherein the first shading rate is different from the second shading rate. The technology marks a dependency of the first thread group on the second thread group.

Dynamic dependency scoreboard for overlapping pixels of primitives

Methods, systems and apparatuses provide for graphics processor technology that determines whether a first cache line allocated for early depth testing overlaps a second cache line allocated for late depth testing, and when the first cache line overlaps the second cache line, switches the first cache line to be allocated for late depth testing, and bypasses an early depth test for the first cache line. The technology can also compare coordinates of the first cache line with the coordinates of the second cache line, where an overlap is determined when coordinates for at least one pixel in the first cache line match coordinates for at least one pixel in the second cache line. Additionally, the technology can also perform early depth testing on each pixel in the first cache line when the first cache line does not overlap any existing cache lines allocated for late depth testing.

Opportunistic late depth testing to prevent stalling for overlapping cache lines

Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.

Processor power management

Methods, systems and apparatuses provide for graphics processor technology that generates attribute plane coefficients based on barycentric coefficients, wherein the attribute plane coefficients are generated on a per polygon basis, and interpolates one or more pixel attributes based on the attribute plane coefficients. In one example, the technology excludes the barycentric coefficients from one or more per pixel operations.

Converting barycentric planes to attribute planes

An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The system may include one or more of a draw call re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more draw calls, a workload re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more work items in an order independent mode, a queue primitive included in at least one of the two or more draw calls to define a producer stage and a consumer stage, and an order-independent executor communicatively coupled to the application processor and the graphics subsystem to provide tile-based order independent execution of a compute stage. Other embodiments are disclosed and claimed.

Order independent asynchronous compute and streaming for graphics

In an example, an apparatus comprises a plurality of execution units, and a first general register file (GRF) communicatively couple to the plurality of execution units, wherein the first GRF is shared by the plurality of execution units. Other embodiments are also disclosed and claimed.

Hierarchical general register file (GRF) for execution block

Briefly, in accordance with one or more embodiments, a processor receives an incoming data stream that includes alpha channel data, and a memory stores an application programming interface (API). The API is to route the alpha channel data to a fixed point blending unit to perform one or more blending operations using fixed point representation of the alpha channel data. The API is further to route the incoming data stream to a floating point blending unit to perform operations involving floating point representation of the incoming data.

Dedicated fixed point blending for energy efficiency

An apparatus to facilitate data intelligent dispatching is disclosed. The apparatus includes one or more processing units including a plurality of execution units (EUs) to execute a plurality of processing threads and collection logic to collect statistics data for threads executed at the processing unit during execution of an application, and dispatch logic to dispatch the threads to be executed at a subset of the plurality of EUs during a subsequent execution of the application based on the statistics data.

Intelligent graphics dispatching mechanism

A control surface tracks an individual cacheline in the original surface for frequent data values. If so, control surface bits are set. When reading a cacheline from memory, first the control surface bits are read. If they happen to be set, then the original memory read is skipped altogether and instead the bits from the control surface provide the value for the entire cacheline.

Frequent data value compression for graphics processing units

Disclosed herein is an apparatus which comprises a plurality of execution units, and a first general register file (GRF) communicatively couple to the plurality of execution units, wherein the first GRF is shared by the plurality of execution units.

Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive data for a current write operation to a memory, determine a number of bits in the received data for the current write operation to the memory which have changed from a previous write operation to the memory and in response to a determination that the number of bits in the received data for the current write operation to the memory which have changed from a previous write operation to the memory exceeds a threshold, to toggle a plurality of bits in the data for the current write operation to create an encoded data set and set an indicator bit to a value which indicates that the plurality of bits have been toggled. Other embodiments are also disclosed and claimed.

Power consumption management for communication bus

Growing community of inventors

Latrobe, CA, United States of America

Eric J Hoekstra