Intel Corporation

Eric J DeHaemer

Malini Krishnan Bhandaru

Vivek Garg

Scott P Bobholz

Ankush Varma

Raghunandan Makaram

Chris Poirier

Krishnakanth Venkata Sistla

Jeremy J Shrall

James R Vash

Stephen H Gunther

Avinash N Ananthakrishnan

Guy M Therien

Herbert H Hum

Leena K Puthiyedath

Brinda Ganesh

Adrian C Moga

Arijit Biswas

Martin Rowland

Ganesh Kumar

Richard Lawrence Carlson

David Bubien

Scott J Erlanger

Michelle M Sebot

Hang T Nguyen

Devadatta V Bodas

Eric R Delano

Guy G Sotomayor

Xiuting C Man

Thi Dang

Krishna K Rangan

Cyprian W Woo

Ian M Steiner

Mark P Seconi

Reid James Riedlinger

Victor Lau

Daniel J Ragland

Matthew M Bace

Michael D Powell

David T Mayo

James Ignowski

Ariel Gur

Don Soltis

Yoav Ben-Raphael

Alexander Gendler

Dean A Mulla

Pak-Lung Seto

Ashish V Choubal

Ilango S Ganga

Viktor D Vogman

Theodore L Willke

Arvind Raman

Brian J Griffith

Christopher Allan Poirier

Eric R DeLano

Manoj Wadekar

Deif N Atallah

Monica C Wong-Chan

Rahul Agrawal

Suresh Chemudupati

Joseph R Doucette

Stanley Chen

Don C Soltis, Jr

Johan Van De Groenendaal

Samuel W Ho

Bruno DiPlacido

Paul A Jacobs

In an embodiment, a processor may include at least one processing engine to execute instructions, and a register interface circuit coupled to the at least one processing engine. The register interface circuit may be to: receive a request to access a register associated with a feature of the processor; determine whether the requested access is authorized based at least in part on an entry of an access structure, the access structure to store a plurality of entries associated with a plurality of features of the processor; and in response to a determination that the requested access is authorized by the access structure, perform the requested access of the register associated with the feature. Other embodiments are described and claimed.

Register interface for computer processor

In one embodiment, a processor includes: a plurality of cores each comprising a multi-threaded core to concurrently execute a plurality of threads; and a control circuit to concurrently enable at least one of the plurality of cores to operate in a single-threaded mode and at least one other of the plurality of cores to operate in a multi-threaded mode. Other embodiments are described and claimed.

System, apparatus and method for configurable control of asymmetric multi-threading (SMT) on a per core basis

A multicore processor may include multiple processing cores that were previously designated as active cores and at least one processing core that was previously designated as a functional spare. The processor may include an interface to receive, during operation of the processor in an end-user environment, a request to change the designation of at least one of the processing cores. The processor may be to store, into a desired cores configuration data structure in response to the request, data representing a bitmask that reflects the requested change, and to execute a reset sequence. During the reset sequence, the processor may activate, dependent on the bitmask, a processing core previously designated as a functional spare, or may deactivate, dependent on the bitmask, a processing core previously designated as an active core. The processor may include a predetermined maximum number of active cores and a predetermined minimum number of functional spares.

Systems and methods for in-field core failover

In one embodiment, a multicore processor includes cores that can independently execute instructions, each at an independent voltage and frequency. The processor may include a power controller having logic to provide for configurability of power management features of the processor. One such feature enables at least one core to operate at an independent performance state based on a state of a single power domain indicator present in a control register. Other embodiments are described and claimed.

Multicore processor with a control register storing an indicator that two or more cores are to operate at independent performance states

Configuring power management functionality in a processor

A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.

Processors having virtually clustered cores and cache slices

Work can be migrated between processor cores. For example, a thread causing a heavy load on a first core can be detected. A power control unit can determine to migrate the thread from the first less-efficient core to the second more-efficient core. The power control unit can request that the first core and the second core transition to a low-power state (e.g., a sleep state, a C6 power state, etc.). The first core can transfer its software context to a first core software context storage, halt and quiesce. The second core can halt and quiesce. The software context from the first core software context storage can be transferred to a second core software context storage of the second core. A processing core identifier of the first core can be assigned to the second core. The power control unit can then request the second core to transition to an active state (such as a C0 state).

Systems, methods and devices for work placement on processor cores

One embodiment of an apparatus includes a semiconductor chip having a processor and an on-die non-volatile storage resource. The on-die non-volatile storage may store different, appropriate performance related information for different configurations and usage cases of the processor for a same performance state of the processor.

Mechanism to provide workload and configuration-aware deterministic performance for microprocessors

In an embodiment, a processor comprises: a plurality of cores each to execute instructions; a plurality of thermal sensors, at least one of which is associated with each of the cores; and a power control unit (PCU) coupled to the cores. The PCU includes a thermal control logic to preemptively throttle a first core by a first throttle amount when a temperature of a second core exceeds at least one thermal threshold. Note that this first core may be preemptively throttled independently of a throttling of the second core and may have a temperature of the first core does not exceed any thermal threshold. Other embodiments are described and claimed.

Adaptive algorithm for thermal throttling of multi-core processors with non-homogeneous performance states

Growing community of inventors

Shrewsbury, MA, United States of America

Eric J DeHaemer