National Semiconductor Corporation

Seagate Technology Incorporated

Eric J Behnke

Robert Wayne Moss

Thomas V Spencer

Randy C Willig

Brett James Pardikes

Anthony Leigh Priborsky

Scott Younger

Thomas B Brightman

Thomas J Skaar

Steve Matson

Todd Robert Beetcher

Craig Shifman

Method and apparatus for managing data transfers. In some embodiments, first and second storage devices respectively include first and second controllers, first and second local memories, and first and second non-volatile memories (NVMs). A virtual controller memory buffer (CMB) is formed from a dedicated portion of each of the first and second local memories for control by a host device. The first controller receives a virtual command set from the host device, and extracts a first local command to transfer data between the host device and the first NVM. In some cases, the second controller also receives the virtual command set and concurrently extracts a different, second local command to transfer data between the host device and the second NVM. Alternatively, the first controller may extract and forward the second local command to the second controller. The first and second NVMs may form an NVMe (Non-Volatile Memory Express) namespace.

Virtual controller memory buffer

Apparatus and method for supplying electrical power to a device. A system on chip (SOC) integrated circuit includes a first region having a processing core and a second region characterized as an always on domain (AOD) power island having a power control block with an energy detector coupled to a host input line. First and second power supply modules respectively supply power to the first and second regions. The second power supply module includes a main switch between the first power supply module and a host input voltage terminal. The power control block opens the main switch to enter a low power mode during which no power is supplied to the first region, and the power control block closes the main switch to resume application of power to the first region responsive to the energy detector detecting electrical energy on the host input line.

PHY based wake up from low power mode operation

Portable internet terminal

A system and method of virtualized audio generation and capture in a computer system is disclosed employing the native central processing unit and a system management mechanism, to generate and capture music and other sound effects, responsive to events occurring in an application program executed by the native central processing unit or to input buffer percentage full signals.

Virtual audio generation and capture in a computer

A computing system having a processor employs an accelerated virtual subsystem architecture which may reside in either the processor or chipset logic circuitry disposed on the motherboard. The accelerated virtualization process employs at least one phantom read register that provides logical status information in response to an I/O read operation or operations--avoiding engagement of the system management mode as fulfillment of the virtualization process. The at least one phantom read register is updated by the virtualization process and supplies the expected response to an application/driver program running on the processor responsive to the execution of an I/O read operation without invocation of an SMI. Preferably, at least one latch is further provided to buffer writes of indexes of index/data write pairs to further avoid engagement of the system management mode as fulfillment for the virtualization process. When the data write of the index/data pair write occurs, application/driver software retrieves the buffered index for use in the virtualization process to virtualize the appropriate behavior. Alternatively, multiple index/data write pairs may be gathered and acted on when a predetermined index value is recognized.

Optimized environments for virtualizing physical subsystems independent

A computer system employs systems and methods that are transparent to the operating system and application programs, for interruption recovery and resynchronization of events including a playback FIFO buffer having an underrun counter that counts the number of audio samples that could not be read from the playback FIFO buffer because the playback FIFO buffer was empty. When the playback FIFO buffer goes empty, an interrupt is asserted to signal the processor to read the underrun counter to determine how many samples it missed and to advance its pointers forward to 're-sync' the data stream. The computer system further preferably includes a capture FIFO buffer to capture samples from an ADC and having an overrun counter that counts the number of audio samples that could not be written to the capture FIFO buffer because the capture FIFO buffer was full. The capture FIFO buffer generates an interrupt to signal the processor to read the overrun counter to determine how many samples it missed and to fill a record buffer with a number of samples equal to the overrun count, wherein each sample has a predetermined value preferably equal to the value of the last input before overrun.

Interrupption recovery and resynchronization of events in a computer

Growing community of inventors

Boulder, CO, United States of America

Eric J Behnke