Lsi Logic Corporation

Lsi Corporation

Eric Hung

Vijendra Kuroodi

Geeta K Desai

Ho-Ming Leung

Mirko Dusan Vojnovic

Alexander Miretsky

Elliot Sowadsky

Remi C Lenoir

Timothy J Wilson

Zoltan Toth

Daniel S Perrin

Norman Sai

An integrated circuit is provided that includes an execution engine and a memory controller. The execution engine is clocked at a first rate and the memory controller is clocked at a second rate that is less than the first rate. Pins on the integrated circuit can transfer data to and from the integrated circuit on both the rising and falling edges of a second clock transitioning at the second clock rate. The integrated circuit is preferably packaged using a lead frame and wire bonds extending from pads on the integrated circuit to corresponding leads. The leads are secured to trace conductors on a surface of a printed circuit board. The board contains no more than two conductive layers separated by a dielectric layer. Thus, an overall electronic system is formed having a board with no more than two conductive layers, an execution engine that receives a first clock signal, a memory controller which receives a second clock signal, and a memory device that sends data to and from the memory controller at twice the rate of the second clock signal. Using a throttled second clock signal allows for less expensive packaging and mounting of packaged integrated circuits on a less expensive PCB, while still maintaining use of a DDR DRAM transfer mechanism.

Low power memory controller with leaded double data rate DRAM package on a two layer printed circuit board

Low power memory controller with leaded double data rate DRAM package arranged on a two layer printed circuit board

An apparatus comprising a first portion, a second portion and a processor. The first portion is configured to generate a count signal in response to a number of oscillations of a clock signal. The first portion is powered by an unswitched power source. The second portion is configured to generate an interrupt signal in response to the count signal and a predetermined stored value. The second portion is powered by a switched power source. The processor is configured to (i) receive the interrupt signal and (ii) generate the switched power.

Real time clock architecture and/or method for a system on a chip (SOC) application

An apparatus comprising a phase lock loop circuit and a control circuit. The phase lock loop circuit configured to generate an output signal having a first frequency in response to (i) an input signal having a second frequency, (ii) a first divider value and (iii) a second divider value. The second divider value may control spread spectrum modulation of the phase lock loop circuit. The control circuit configured to generate the second divider value in response to (i) the output signal and (ii) a programmable control signal.

Integrated clock generator with programmable spread spectrum using standard PLL circuitry

A memory controller is provided and a method for transferring data between the memory controller and a memory device. The memory controller can be implemented on an integrated circuit that also contains an execution unit. The execution unit can be clocked at a first clock rate, whereas the memory controller can be selectively clocked at either the first clock rate or a second clock rate that is approximately one-half frequency of the first clock rate. By clocking the memory controller at either the first clock rate or the second clock rate, the memory controller can accommodate different types of semiconductor memory. For example, the memory controller can control single data rate (SDR) DRAM memory if it is clocked at a first clock rate. Conversely, the memory controller can control double data rate (DDR) DRAM memory if it is clocked at approximately one-half the first clock rate. By selectively clocking the memory controller at different clocking rates, the memory controller need not be modified in hardware, yet can accommodate different memory devices by allowing a user to simply plug one type of memory into a receptacle rather than another depending on the cost constraints and user application. Therefore, the memory controller is adaptable during a power-on reset in which the computer system is initialized to automatically receive and control different types of memory selected by a user.

Low power memory controller that is adaptable to either double data rate DRAM or single data rate synchronous DRAM circuits

A memory module is provided as well as a method for forming a memory module. The memory module includes a printed circuit board having opposed first and second outside surfaces. At least one via can extend through the printed circuit board and couples a conductor on one outside surface to a conductor on another outside surface. A semiconductor memory device on one of those outside surfaces can thereby be connected to one end of the via, with another semiconductor memory device on the opposing outside surface connected to the other end of the via. Preferably, the pair of memory devices are placed on a portion of each respective outside surface so that they essentially align in mirrored fashion with each other. Accordingly, any vias which extend from the footprint of one memory device will take the shortest path to the footprint of the other memory device, with the stubs between the footprint and the via being of essentially the same length and relatively short. The printed circuit board preferably has no more than four conductive layers dielectrically spaced from each other. Two layers are reserved for the opposing outer surfaces, and two layers carrying power and ground signals are embedded within the board. The memory devices are preferably DDR SDRAMs connected to each other as well as a memory controller, each of are placed and maintained upon a single printed circuit board.

Memory module having mirrored placement of DRAM integrated circuits upon a four-layer printed circuit board

Growing community of inventors

San Jose, CA, United States of America

Eric Hung