Taiwan Semiconductor Manufacturing Comp. Ltd.

Eric Huang

Ruey-Hsin Liu

Tsung-Yi Huang

Fu-Hsin Chen

Chyi-Chyuan Huang

Bao-Ru Young

Wei Cheng Wu

Harry Hak-Lay Chuang

Po-Nien Chen

Puo-Yu Chiang

Chi-Hsun Hsieh

Chun Lin Tsai

Chih-Chang Cheng

Shun-Liang Hsu

Hsiao-Chin Tuan

Chih-Wen Yao

Fu Chin Yang

Chia-Chin Shen

Chung-Yeh Wu

An exemplary integrated circuit comprises: a first device gate disposed over the first device region, the first device gate comprising a first interfacial layer and a first dielectric layer; a second device gate disposed over the second device region, the second device gate comprising a second interfacial layer and a second dielectric layer; and a third device gate disposed over the third device region, the third device gate comprising a third interfacial layer and a third dielectric layer, wherein the first interfacial layer, the second interfacial layer, and the third interfacial layer are different from each other in at least one of a thickness and an interfacial material.

Circuit incorporating multiple gate stack compositions

A method including providing a substrate having a first region, a second region, and a third region defined thereupon. A first interfacial layer is formed over the first region, the second region, and the third region. The first interfacial layer is etched to remove a portion of the first interfacial layer from the first region and a portion of the first interfacial layer from the second region. Etching of the first interfacial layer defines a gate stack within the third region. After the etching of the first interfacial layer, a second interfacial layer is formed over at least a portion of the second region. The second interfacial layer is etched to define a gate stack within the second region. After the etching of the second interfacial layer, a third interfacial layer is formed on the substrate over at least a portion of the first region to define a gate stack within the first region.

Methods of fabricating multiple gate stack compositions

A method of forming a device includes forming a buried well region of a first dopant type in a substrate. A well region of the first dopant type is formed over the buried well region. A first well region of a second dopant type is formed between the well region of the first dopant type and the buried well region of the first dopant type. A second well region of the second dopant type is formed in the well region of the first dopant type. An isolation structure is formed at least partially in the well region of the first dopant type. A first gate electrode is formed over the isolation structure and the second well region of the second dopant type.

Method of forming high voltage device

An integrated circuit having multiple different device gate configurations and a method for fabricating the circuit are disclosed. An exemplary embodiment of forming the circuit includes receiving a substrate having a first device region, a second device region, and a third device region. A first interfacial layer is formed over at least a portion of each of the first device region, the second device region, and the third device region. The first interfacial layer is patterned to define a gate stack within the third device region. A second interfacial layer is formed over at least a portion of the second device region. The second interfacial layer is patterned to define a gate stack within the second device region. A third interfacial layer is formed over at least a portion of the first device region. The third interfacial layer defines a gate stack within the first device region.

Method of fabricating multiple gate stack compositions

A high voltage (HV) device includes a well region of a first dopant type disposed in a substrate. A first well region of a second dopant type is disposed in the well region of the first dopant type. An isolation structure is at least partially disposed in the well region of the first dopant type. A first gate electrode is disposed over the isolation structure and the first well region of the second dopant type. A second well region of the second dopant type is disposed in the well region of the first dopant type. The second well region of the second dopant type is spaced from the first well region of the second dopant type. A second gate electrode is disposed between and over the first well region of the second dopant type and the second well region of the second dopant type.

High voltage devices and methods of forming the high voltage devices

A semiconductor structure includes a semiconductor substrate of a first conductivity type; a pre-high-voltage well (pre-HVW) in the semiconductor substrate, wherein the pre-HVW is of a second conductivity type opposite the first conductivity type; a high-voltage well (HVW) over the pre-HVW, wherein the HVW is of the second conductivity type; a field ring in the HVW and occupying a top portion of the HVW, wherein the field ring is of the first conductivity type; an insulation region over and in contact with the field ring and a portion of the HVW; a gate electrode partially over the insulation region; a drain region in the HVW, wherein the drain region is of the second conductivity type; and wherein the HVW horizontally extends further toward the drain region than the pre-HVW; and a source region adjacent to, and on an opposite side of the gate electrode than the drain region.

Lateral power MOSFET with high breakdown voltage and low on-resistance

A semiconductor structure includes a semiconductor substrate of a first conductivity type; a pre-high-voltage well (pre-HVW) in the semiconductor substrate, wherein the pre-HVW is of a second conductivity type opposite the first conductivity type; a high-voltage well (HVW) over the pre-HVW, wherein the HVW is of the second conductivity type; a field ring of the first conductivity type occupying a top portion of the HVW, wherein at least one of the pre-HVW, the HVW, and the field ring comprises at least two tunnels; an insulation region over the field ring and a portion of the HVW; a drain region in the HVW and adjacent the insulation region; a gate electrode over a portion the insulation region; and a source region on an opposite side of the gate electrode than the drain region.

Breakdown voltages of ultra-high voltage devices by forming tunnels

A semiconductor structure includes a semiconductor substrate of a first conductivity type; a pre-high-voltage well (pre-HVW) in the semiconductor substrate, wherein the pre-HVW is of a second conductivity type opposite the first conductivity type; a high-voltage well (HVW) over the pre-HVW, wherein the HVW is of the second conductivity type; a field ring of the first conductivity type occupying a top portion of the HVW; and a tunnel of the first conductivity type in the pre-HVW and the HVW, and electrically connecting the field ring and the semiconductor substrate.

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Jhubei, Taiwan

Eric Huang