Cadence Design Systems, Inc.

Rambus Inc.

Eric Harris Naviasky

Thomas Evan Wilson

William Pierce Evans

Stephen T Williams

Michael M Hufford

Ling Chen

Anthony Caviglia

Fuyue Wang

Jianyun Zhang

Ali Ulas Ilhan

Michelle LeRoux Williams

Santiago Luis Bortman

Carl A Ramsey

Loren Blair Reiss

Guillaume Fortin

Mathieu Gagnon

Fred Staples Stivers

Julien Faucher

Benjamin Louis Heilmann

Jim Brown

Chris Moscone

Hugh Thompson

Michael Casas

Martin J Mengele

Tony L Caviglia

Sambarta Rakshit

Rajagopal Vijayaraghavan

Jeremy Lubkin

Alessandro Piovaccari

Timothy Henricks

A set of encoders within a transmitter (TX) physical layer (PHY) encode incoming data using a predefined encoder scheme by translating multiple data segments into a set of balanced bit sequences. Each data segment comprises a first number of bits and each balanced bit sequence comprises a second number of bits. A data striping component distributes the set of balanced bit sequences to a set of serializers by routing bits from particular bit positions in each balanced bit sequence to a corresponding serializer. The set of serializers generates serialized data based on the set of balanced bit sequences.

Encoding and striping technique for DC balancing in single-ended signaling

Various embodiments described herein provide a multiple injection lock ring-based PI that can inject a plurality of clock signals, of different phases, at injection points disposed along the ring chain of the PI and lock phase to those received clock signals (injected clock signals). For instance, an embodiment described herein may provide a multiple injection lock ring-based PI that permits double injection, triple injection, or the like, of clock signals external into the PI.

Multiple injection lock ring-based phase interpolator

Aspects of the present disclosure include a dual path phase locked loop (PLL) circuit with a switched capacitor filter topology along with systems, method, devices, and other circuits related thereto. The dual path PLL circuit includes an integral path and a proportional path. Both the integral path and proportional path include a charge pump and a loop filter. The outputs of a phase frequency detector (PFD) are sent to both charge pumps. The output of the integral path charge pump is connected to a capacitor, and the voltage on capacitor is used as the integral path control voltage for a voltage-controlled oscillator (VCO). A switched capacitor network is connected to the output of the proportional path charge pump and used to generate the proportional path control voltage for the VCO. Together, the two control voltages dictate the VCO's output frequency.

Dual path phase-locked loop circuit

Aspects of the present disclosure include systems, methods, devices, and circuits for fast settling of a bias node. Consistent with some embodiments, a bias circuit may include a successive-approximation-register-analog-to-digital converter (SAR-ADC) based settling loop configured to perform a fast settling process for a heavily loaded bias node. The SAR-ADC based loop performs a SAR-ADC process that includes measuring a reference signal to determine a number of cells in a capacitor array that are involved in a charge sharing process while simultaneously completing the settling process for the bias node.

Fast settling bias circuit

A system and a method for detecting a low-frequency periodic signal (LFPS) include at least one comparator performing a threshold comparison on an analog input signal over a period of time. A sampling circuit generates digital signals by sampling an output of the at least one comparator. A digital detection circuit applies a set of detection rules to the digital signals. The detection rules are configured to detect a presence or an absence of an LFPS based on predefined criteria concerning characteristics of the digital signals.

Low-frequency periodic signal detector

Embodiments relate to systems, methods and computer readable media to enable design and creation of receiver circuitry One embodiment is a receiver apparatus comprising a first resistor connected to a first receiver input, a first N-type metal oxide semiconductor (NMOS) field effect transistor (FET), a second NMOS FET, a trans-impedance amplifier wherein an input terminal of the trans-impedance amplifier is connected to a drain terminal of the second NMOS FET, and a complementary metal oxide semiconductor (CMOS) logic gate. Additional embodiments including other circuitry, associated methods, and media comprising instructions associated with generation of circuit design files are also described.

Methods and devices for a memory interface receiver

Aspects of the present disclosure include a frequency-to-current (F2I) circuit and systems, methods, devices, and other circuits related thereto. The F2I circuit is implemented with a delta-modulator-based control loop to settle and maintain an operating point on a bias node. The control loop provides an integral of an output of a comparator, and the comparator compares it to a self-built voltage reference. Upon powering on the circuit, an integrator in the control loop starts to integrate the charge on both a bias voltage and an internal voltage to provide a settling process for the internal voltage to approximate the reference voltage and for the bias voltage to approximate a predetermined operating point of the bias node. After the circuit has settled, the comparator's output charge toggles and the internal voltage and bias voltage become sawtooth-like waveforms at the reference voltage and operating points, respectively.

Frequency to current circuit

Embodiments relate to systems, methods and computer readable media to enable design and creation of memory driver circuitry using a voltage translation capacitor. One embodiment is high speed level translation memory driver apparatus comprising a plurality of field effect transistors (FETs), complementary metal oxide semiconductor (CMOS) logic gates to drive the FETs, and a voltage translation capacitor with a first terminal of the voltage translation capacitor connected to an output of a second CMOS logic gate and a second terminal of the voltage translation capacitor connected to a gate terminal of a first P-type FET. Additional embodiments including other circuitry, associated methods, and media comprising instructions associated with generation of circuit design files are also described.

Methods and devices for a DDR memory driver using a voltage translation capacitor

A system and method are provided for selectively coupled parasitic compensation for voltage offset in an electronic circuit. At least one compensation cell is coupled to an input stage for the circuit. The compensation cell includes an isolation node disposed in spaced manner from control and sampling nodes defined by the input stage. The isolation node is configured to form first and second parasitic capacitances respectively with the control and sampling nodes during system operation. An offset switch is coupled to the isolation node and selectively set between first and second switching states. The offset switch selectively either maintains or interrupts a series coupling of the first and second parasitic capacitances between the control and sampling nodes; and, the sampling node is thereby adaptively adjusted in voltage by a predetermined portion of a control signal applied to the control node.

System and method for selectively coupled parasitic compensation for input referred voltage offset in electronic circuit

A full wave rectifier () for use as part a differential signal detector () detects both high and low envelopes of differential signals (RX, RX) at a pair of differential inputs () and provides a sense signal (V) at an output () thereof. The differential signal detector () includes both the full wave rectifier () and a voltage reference source () having a circuit architecture in common, and a comparator for comparing the sense signal (V) with a reference voltage (V. The circuit configuration of both the full wave rectifier () and the voltage reference source () include first and second differential input circuits (andand) each including a pair of field effect transistors (andand) of different conductivity type having respective source terminals () coupled together.

Differential signal detector and full wave rectifier circuit thereof with common mode signal rejection

A system and method are provided which incrementally samples and delays a signal passed through a transmission channel thereto. A receiver section is provided with a delay stage including a sample storage portion having a plurality of capacitors. A switch portion selectively switches the capacitors to respectively store incremental samples of the signal received through the channel. A clock source is provided to generate a plurality of periodic clock signals progressively shifted by a predefined clock phase increment. The clock source drives the switch portion to synchronously cycle the capacitors through at least sample and readout modes of operation, which are mutually offset in time by a preselected number of clock phase increments. The received signal is collectively reconstructed from the incremental samples of the capacitors, such that the reconstructed signal is delayed by the preselected number of clock phase increments.

System and method for synchronously adjusted delay and distortion mitigated recovery of signals

In a clock recovery system, a phase detector detects a phase error in an incoming data signal, which it outputs as a differential pair of voltage signals representing positive and negative errors, respectively. A proportional filter generates a proportional offset from the phase error, also as a differential pair of voltage signals. An integral filter generates an integral offset from the proportional offset, using positive and negative voltage controlled oscillators to generate oscillating integral offset signals, and an accumulator to increment or decrement a digital counter for each cycle of the integral offset signals. A first, fractional phase interpolator operating over a ninety-degree range adjusts the phase of an initial clock signal to generate an intermediate clock signal, according to the proportional offset. A second phase interpolator adjusts the phase of the intermediate clock signal to generate an adjusted clock signal, according to the integral offset.

Hybrid analog/digital clock recovery system

A time to digital converter with a successive approximation architecture () and a method thereof is provided. The time to digital converter () includes successive approximation analog to digital converter circuitry () configured for converting the differential voltage established in the digital to analog converter () of the successive approximation analog to digital converter circuitry () to a digital representation thereof, where the differential voltage corresponds to a measured time period representing a time difference between receipt of leading edges of two signals. Time to digital converter () may incorporate a current switching unit (') having a plurality of current switching circuits (--) arranged in parallel to increase the precision of digital time output of time to digital converter (). The plurality of current switching circuits (--) can be selectively enabled to alter the sensitivity of the time to digital converter ().

Time to digital converter with successive approximation architecture

A system and method are provided for boosting a selective portion of a drive signal for chip-to-chip transmission across an interconnection interface. The system includes a driver unit generating a drive signal responsive to an input data signal. The drive signal is provided on to at least one output node for transmission through the device interconnection interface, and defines a peak amplitude during a drive period. A boosting unit is coupled to the driver unit for selectively boosting a portion of the drive signal. The boosting unit actuates responsive to the input data signal to selectively apply a boost signal in self-timed manner to the drive signal, so as to thereby augment the drive signal in amplitude over a selected portion of the drive period thereof. In this manner, the boosting unit maintains the peak amplitude of the drive signal at or above a predetermined level throughout the drive period.

System and method for boosting a selective portion of a drive signal for chip-to-chip transmission

A system and method are provided for augmenting frequency tuning resolution in an L-C oscillatory circuit which comprises a source of electrical energy, and a tuned section energized by said source of electrical energy for oscillatory conduction of a resonant current therethrough. The tuned section includes an inductor portion extending in substantially looped manner between first and second connection points to define at least one turn. A primary capacitor portion is connected across at least a primary segment of the conductive member delineated by the first and second connection points. The tuned section further includes a secondary capacitor portion connected across a secondary segment of the conductive member intermediately tapped from the primary segment. The secondary capacitor portion defines a base tuning capacitance for the tuned section, which is down-converted to a fine tuning capacitance when reflected to a calibration capacitance of the primary capacitor portion for adjustable combination therewith.

Growing community of inventors

Ellicott City, MD, United States of America

Eric Harris Naviasky