Other

Apple Inc.

Transmeta Corporation

P.a. Semi, Inc.

Eric Hao

Po-Yung Chang

Brett Coon

John P Banning

Sudarshan Kadambi

Tse-Yu Yeh

Guillermo Juan Rozas

Alexander Klaiber

A method and system of instruction modification. A first machine language instruction, which may comprise a plurality of discrete instructions, is fetched. Responsive to a trigger pattern in the first machine language instruction, a segment of the first machine language instruction is modified. Information can be substituted into the segment based on specifics outlined in the trigger pattern. Alternatively, information can be combined with the segment via logical and/or arithmetic operations. Modification of the segment produces a second machine language instruction that is executed by units of the processor. In one embodiment, information may be taken from a queue and used to replace data from the segment. How information is taken from the queue and how the information so taken is used to replace fields of the segment are defined by the trigger pattern.

System and method of instruction modification

In one embodiment, a processor comprises a circuit coupled to receive an indication of a memory operation to be executed in the processor. The circuit is configured to predict whether or not the memory operation is misaligned. A number of accesses performed by the processor to execute the memory operation is dependent on whether or not the circuit predicts the memory operation as misaligned. In another embodiment, a misalignment predictor is coupled to receive an indication of a memory operation, and comprises a memory and a control circuit coupled to the memory. The memory is configured to store a plurality of indications of memory operations previously detected as misaligned during execution in a processor. The control circuit is configured to predict whether or not a memory operation is misaligned responsive to a comparison of the received indication and the plurality of indications stored in the memory.

Misalignment predictor

In one embodiment, a processor comprises a prediction circuit and another circuit coupled to the prediction circuit. The prediction circuit is configured to predict whether or not a first load instruction will experience a partial store to load forward (PSTLF) event during execution. A PSTLF event occurs if a plurality of bytes, accessed responsive to the first load instruction during execution, include at least a first byte updated responsive to a previous uncommitted store operation and also include at least a second byte not updated responsive to the previous uncommitted store operation. Coupled to receive the first load instruction, the circuit is configured to generate one or more load operations responsive to the first load instruction. The load operations are to be executed in the processor to execute the first load instruction, and a number of the load operations is dependent on the prediction by the prediction circuit.

Partial load/store forward prediction

A method and system for expanding an instruction set by decoding an instruction located at a particular address using one or more of those address bits in conjunction with the instruction word.

Method and system for using one or more address bits and an instruction to increase an instruction set

The speed of processing of a sequence of indirect branch instructions in a pipelined processor is increased by overlapping the latencies in the sequence of indirect branch instructions. The architecture of a digital processor is modified to include a link pipe system that allows the sequence of branch addresses required by the indirect branches to be written to a single location within the processor, and to be read from a single location in the processor. The link pipe system contains a plurality of registers ( & ) for storage of respective branch target addresses. Each WRITE of a branch address is automatically directed ( ) to individual registers within the link pipe system for storing the respective branch addresses; and each READ of a branch address is automatically directed ( ) to the register containing the earliest WRITE of an address that was not previously read by the processor, whereby branch target addresses are retrieved on a &ldquo;first in, first out&rdquo; basis.

Growing community of inventors

Cupertino, CA, United States of America

Eric Hao