Texas Instruments Corporation

Eric H Warninghoff

Alan G Merriam

Jeffrey Alan West

Kezhakkedath Ramunni Udayakumar

Rick A Faust

Bhaskar Srinivasan

Haowen Bu

Brian Goodlin

Manoj K Jain

An integrated circuit and method comprising an underlying metal geometry, a dielectric layer on the underlying metal geometry, a contact opening through the dielectric layer, an overlying metal geometry wherein a portion of the overlying metal geometry fills a portion of the contact opening, and an oxidation resistant barrier layer disposed between the underlying metal geometry and overlying metal geometry. The oxidation resistant barrier layer is formed of TaN or TiN with a nitrogen content of at least 20 atomic % and a thickness of at least 5 nm.

Oxidation resistant barrier metal process for semiconductor devices

Deposition of lead-zirconium-titanate (PZT) ferroelectric material over iridium metal, in the formation of a ferroelectric capacitor in an integrated circuit. The capacitor is formed by the deposition of a lower conductive plate layer having iridium metal as a top layer. The surface of the iridium metal is thermally oxidized, prior to or during the deposition of the PZT material. The resulting iridium oxide at the surface of the iridium metal is very thin, on the order of a few nanometers, which allows the deposited PZT to nucleate according to the crystalline structure of the iridium metal rather than that of iridium oxide. The iridium oxide is also of intermediate stoichiometry (IrO), and reacts with the PZT material being deposited.

Adhesion of ferroelectric material to underlying conductive capacitor plate

Growing community of inventors

Allen, TX, United States of America

Eric H Warninghoff