Lara Technology, Inc.

Cypress Semiconductor Corporation

Netlogic Microsystems, Inc

Nvidia Corporation

Other

Suvolta, Inc.

Eric H Voelkel

Stefan P Sywyk

Roger J Bettman

Anita X Meng

Jun Yang

Lei Wang

Stephen Felix

Srinivasan Venkatachary

Ge Yang

Spencer Montgomery Gold

Hua Chen

Hwong-Kwo Lin

Greg J Landry

Jing Guo

Andrew J Wright

Andreas J Gotterba

Robert M Reinschmidt

Rochan Sankar

Jayan R Ramankutty

Haiyan Gong

Karthik Natarajan

Jason Golbus

Zhenye Jiang

Beibei Ren

Michael H Miller

Sow T Chu

A subsystem configured to select the power supply to a static random access memory cell compares the level of a dedicated memory supply voltage to the primary system supply voltage. The subsystem then switches the primary system supply to the SRAM cell when the system voltage is higher than the memory supply voltage with some margin. When the system voltage is lower than the memory supply voltage, with margin, the subsystem switches the memory supply to the SRAM cell. When the system voltage is comparable to the memory supply, the subsystem switches the system voltage to the SRAM cell if performance is a prioritized consideration, but switches the memory supply to the SRAM cell if power reduction is a prioritized consideration. In this manner, the system achieves optimum performance without incurring steady state power losses and avoids timing issues in accessing memory.

Power savings via selection of SRAM power source

A system and method are provided for generating an adaptive clock signal, configured to track prevailing operating conditions within an integrated circuit. The method comprises transmitting a first signal edge to a row of cells within a memory instance, waiting for two or more selected cells within the row of cells to propagate corresponding responses based on the first signal edge, and generating a memory delay signature signal edge based on the corresponding responses. The adaptive clock signal is generated based on the delay signature signal edge.

System and method for a dynamic voltage controlled oscillator

A method for operating an SRAM cell comprises, during a read operation, forward biasing an N-well of a first and second pull-up transistor, and forward biasing a P-well of a first and second pull-down transistor and a first and second access transistor. The method further comprises, during a write operation, zero or reverse biasing an N-well of a first and second pull-up transistor, and forward biasing a P-well of a first and second pull-down transistor and a first and second access transistor. The method further comprises, during an idle state, zero biasing an N-well of a first and second pull-up transistor and zero biasing a P-well of a first and second pull-down transistor and a first and second access transistor. In addition, one or more rows or columns of memory cells may receive a bias voltage.

Swapped-body RAM architecture

A ternary content addressable memory (TCAM) cell () can include two memory elements (-and-) with a single bit line (-and-) per memory element. A TCAM cell () can also include a compare stack () and two word lines (and) that can connect to each memory element (-and-). The memory elements (-and-) can include SRAM type memory cells with one of two data terminals connected to a pre-write potential (Vpre, which can be a ground potential, or the like). Write operations can include pre-setting the data values of memory elements (-and-) to the pre-write potential prior to providing write data via the bit lines (-and-).

Content addressable memory (CAM) cell bit line architecture

A CAM and method for operating a CAM are presented. Copies of a CAM database are duplicated and placed in a first set of CAM locations and a second set of CAM locations. An error detector is used to determine false matches in the case of soft errors within the entries producing those false matches. While the entries producing a match should have the same index location, errors might cause those match lines to have an offset. If so, the present CAM, through use of duplicative sets of CAM locations, will detect the offset and thereafter the values in each index location that produces a match, along with the corresponding parity or error detection encoding bit(s). If the parity or error detection encoding bit(s) indicate an error in a particular entry, then that error is located and the corresponding entry at the same index within the other, duplicative set of CAM locations is copied into the that erroneous entry. Since duplicative copies are by design placed into the first and second sets of CAM locations, whatever value exists in the opposing entry can be written into the erroneous entry to correct errors in that search location. The first and second sets of CAM locations are configurable to be duplicative or distinct in content, allowing error detection and correction to be performed at multiple user-specified granularities. The error detection and correction during search is backward compatible to interim parity scrubbing and ECC scan, as well as use of FNH bits set by a user or provider.

Error correcting content addressable memory

A method and an apparatus to generate static logic level outputs without a direct connection from a MOS transistor gate to either a power supply or ground supply are described. The apparatus may include a first circuit comprising a static logic level output. The apparatus may further include a second circuit coupled to the first circuit to drive the first circuit. The second circuit may comprise at least one of a latch and a feedback device.

Method and an apparatus to generate static logic level output

A content addressable memory (CAM) device () can equalize a potential between a match line () and corresponding pseudo-supply (PVSS) line () in a pre-sense operation. In a sense operation, a sensing device (P) can determine a match condition exists when the match line () potential varies from the PVSS line () potential. Complementary compare data lines (CD and BCD) can be equalized with one another in a pre-sense operation, while one compare data line (CD or BCD) can be equalized with bit lines (BBand/or BB) in the sensing operation.

Sense amplifier architecture for content addressable memory device

A sense amplifier for a content addressable memory (CAM) device can utilize charge sharing between a match line and a pseudo-supply line to indicate a mis-match indication. A sense amplifier () can include match line () that can be precharged to a high supply potential (VCC), a sense node (), and a pseudo-VSS (PVSS) line () that can be precharged to a low supply potential (VSS). In a match result, match line () can remain precharged, keeping sense device (P) turned off, and sense node () remains low, generating a low output signal (SAOUT). In a mis-match result, match line () and sense node () can be equalized. A resulting drop in match line () potential can turn on sense device (P), and sense node () can be pulled high. As a result, output signal (SAOUT) can be driven high.

Sense amplifier circuit for content addressable memory device

According to one embodiment, a content addressable memory (CAM) ( ) can include a number of ordinary rows ( - to -n) that provide ordinary match indications (Match to Matchn) as well as redundant rows ( - and - ) that can provide redundant match indications (RMatch and RMatch ). If an ordinary row ( - to -n) is defective, a redundancy multiplexer ( - to -n) can be switched to provide a redundant match indication (RMatch and RMatch ) as an input to a priority encoder ( ) instead of the ordinary match indication from the defective ordinary row.

Content addressable memory having redundancy capabilities

A content addressable memory (CAM) ( ) can include a number of CAM entries ( - to -n). Match indications from CAM entries ( - to -n) and mismatch indications from complementing circuits ( - and -n) can be supplied to a switching circuit ( ). Mismatch indications can indicate if an entry mismatches data when compared with a comparand ( ). In one mode of operation, a switching circuit ( ) can provide match indications on a number of switch outputs (SW to SWn). In another mode of operation, switching circuit ( ) can provide mismatch indications on a number of switch outputs (SW to SWn).

Method and apparatus for content addressable memory test mode

According to one embodiment, a content addressable memory (CAM) ( ) can include a number of CAM entries ( - to -n) and corresponding status stores ( - and -n). Match indications from the CAM entries ( - to -n) and status information from status stores ( - and -n) can be supplied to a switching circuit ( ). Status information can indicate if an entry stores valid or invalid data. In one mode of operation, the switching circuit ( ) can provide match indication values on a number of switch outputs (SW to SWn). In another mode of operation, the switching circuit ( ) can provide status information on a number of switch outputs (SW to SWn).

Content addressable memory having prioritization of unoccupied entries

According to one embodiment, a content addressable memory (CAM) can include at least one match line ( ), series-coupled transistor pairs comprising match transistors ( - to -n) and switch devices ( - to -n), bit match indicator signals ( - to -n), mask cell value signals ( - to -n), a match line precharge limiting device ( ), a match line precharge control device ( ) and an amplifier circuit ( ). This configuration can allow for the regulation of the match line ( ) discharge path through a discharge control device ( ) and a match indication feedback device ( ). This, in turn, can allow for match line ( ) precharging while at least one of the bit match indicator signals ( - to -n) is in an intermediate, or approximately half-VDD, level that is consistent with relatively low power precharging of the applied comparands. As such, the pseudo-VSS ( ) line control may prevent a static current path from developing during the precharge scenario described above by directly controlling the path between the pseudo-VSS ( ) line and the circuit ground supply.

Content addressable memory having reduced current consumption

A content addressable memory that may have reduced charge consumption when switching compare lines is disclosed. According to one embodiment, a content addressable memory (CAM) ( ) with paired compare lines (CMP and CMP&bsol;) can include an equalization circuit ( ) between the two compare lines (CMP and CMP&bsol;). An equalization circuit ( ) can enter a low-impedance mode when an equalization control signal (EQU&bsol;) is in one state and enter a high-impedance mode when an equalization control signal (EQU&bsol;) is in another state. An equalization control signal (EQU&bsol;) may be governed by an output pulse of a transition detector ( ).

Content addressable memory having compare data transition detector

A CAM cell array ( ) that can provide a longest prefix matching operation without necessarily requiring data values to be stored in a particular order. A comparand value can be applied to a CAM cell array ( ) to generate ternary match indications. The mask/prefix data values of ternary match indications can be combined to generate a longest prefix value. The longest prefix value can be compared with the mask/prefix data values of the ternary match indications to indicate a data value having a longest prefix match with the comparand value.

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Ben Lomond, CA, United States of America

Eric H Voelkel