International Business Machines Corporation

Eric H Stelzer

Gary B Hoch

Serafin J Garcia, Jr

Donald G Williams

Robert Chih-Tsin Eng

Frederick Charles Yentz

Rex E McCrary

Mark G McDonald

Michael S Gatson

John W Galella

DMA adapters which perform programmed data transfer operations in response to descriptors are programmed by information in the same descriptors (and adapter logic responsive to that information) to perform various ancillary control functions relative to addressable I/O devices that conventionally would be addressed and controlled directly by a host (higher level) system processor (e.g., the processor that prepares the descriptors). The ancillary control functions are variable programmably in number (e.g., in the disclosed embodiment, one descriptor can define 0, 1 or 2 discrete ancillary control operations) and effects produced by each operation are programmably variable (e.g., ancillary operation can be used by the adapter to alter states of addressed devices; for example, to prepare a device that has been transferring data in one direction, in a half-duplex mode, for transferring data in the opposite direction, or to switch to a full duplex mode, etc.). These functions hitherto have imposed significant processing burdens on the host processor and functional constraints on the adapters and devices; typically, constraints requiring the adapter and one or more devices to be idled for the time required by the host to condition the device(s). Accordingly, delegation of these functions to the adapter, allows them to be carried out without idling of any system elements and while the host is otherwise productively occupied. Also, such delegation creates new applicational possibilities; e.g., having an adapter linked to a communication channel react to remotely originated signals and set up operations tightly coordinated in real time to previously executed operations (for example, retransmission of data previously received with detected error).

Computer I/O adapters for programmably varying states of peripheral

Disclosed method and apparatus allow for balanced usage of resources in dual bus computing systems wherein: (1) principal resources of the system--including a processor, a local bus, local bus controls, and a memory subsystem--are contained in a single system unit (e.g. a card); (2) devices are coupled to the system unit and to each other through a device communications bus that is also accessible to the processor of the system unit; (3) the system processor is required to have principal access to the local bus, as a 'System Bus Master', for time critical functions such as memory refresh; and (4) the devices include one or more devices that are required to have controlling access to the resources of the system unit, and for that purpose are required to have controlling access to the local bus as Alternate Bus Master entities. The disclosed arrangement allows an Alternate Bus Master operating in a burst mode, in which several cycles of data transfer may occur consecutively, to have continuous access to the local bus after a single signal handshaking exchange with the local bus controls; subject to over-riding conditions which ensure timely accomplishment of the time critical functions controlled by the processor/System Bus Master. The over-riding conditions are detected by special logic that acts, when necessary, to interrupt Alternate Bus Master access to the local bus without affecting the state of connection between the respective Alternate Bus Master and the communications bus.

Providing alternate bus master with multiple cycles of bursting access

A processor stores descriptors without explicit linkages, in non-contiguous memory locations, and sequentially hands them off to an adaptor which manages scheduling and processing of data transfers defined by the descriptors. Each descriptor is handed off in a request signalling process in which the processor polls the availability of a request register in the adaptor, and writes the address of a respective descriptor to that register when it is available. The adapter then schedules processing of the descriptor whose address is in the request register. The adapter manages a 'Channel Descriptor Table' (CDT), which defines the order of processing of descriptors designated by the requests. In effect, the CDT defines a linked list queue into which the adapter installs descriptors, in the sequence of receipt of respective requests. Using the CDT information, the adapter retrieves successively queued descriptors and controls performance of operations (data transfer or other) defined by them. Accordingly, descriptors in the queue are retrieved and respectively defined operations are performed, in the order of receipt of respective requests; as if the descriptors had been stored by the processor with explicit linking and chaining associations and handed off to the adapter as an explicitly chained set of descriptors. In a preferred embodiment, a 'multichannel adapter unit' (MAU), directing data transfers relative to multiple channels, contains one request register for all channels and a separate CDT and 'request address port' dedicated to each channel. Requests accompanied by addresses designating these ports are 'funneled' through the request register to CDT queues of respective channels. The processor can effectively remove a descriptor from any CDT queue, without potentially compromising handling of data transfers defined by other descriptors in the queue, by writing a 'skip code' to the descriptor. Upon retrieving a descriptor with a skip code, the adapter automatically skips the operation defined by that descriptor and chains to a next descriptor (if the queue defined by the CDT is not empty).

Adapters with descriptor queue management capability

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Boca Raton, FL, United States of America

Eric H Stelzer