Ltx Corporation

Eric H Rosenfeld

Phillip D Burlison

Mark E Deome

Tommie Edward Berry

Christopher Joel Hannaford

David W Curry

David Menis

H Neil Kelly

Jeffrey H Perkins

Edward J Terrenzi

Kenneth J Lanier

Roger W Blethen

Michael Carlyle Davis

Donald Vick Organ

Michael Gordon Davis

An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patterns to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns. A tester computer supervises the application of digital, analog, and memory test signals from the digital, analog, and memory test circuitry to the device under test such that signals applied to the device under test can be solely digital test signals, solely analog test signals, solely memory test signals, or mixed digital, analog, and memory test signals. The test head, the digital test circuitry, the analog test circuitry, the memory test circuitry, and the computer are operable as a single platform.

Single platform electronic tester

An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patters to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns. A tester computer supervises the application of digital, analog, and memory test signals from the digital, analog, and memory test circuitry to the device under test such that signals applied to the device under test can be solely digital test signals, solely analog test signals, solely memory test signals, or mixed digital, analog, and memory test signals. The test head, the digital test circuitry, the analog test circuitry, the memory test circuitry, and the computer are operable as a single platform.

A local trigger signal generator is provided for each of a plurality of test instruments in a test system. The disclosed test system includes a master clock generator that defines a start time t.sub.0 and generates a periodic master clock signal characterized by a master clock oscillation frequency f.sub.mc and a corresponding period T.sub.mc. The master clock generator generates a clock network signal that is representative of the master clock signal and the start time t.sub.0. The system further includes a set of n test instruments TIN1, TIN2, . . . TINn. An ith one of the test instruments TINi includes a local clock receiver for receiving the clock network signal and defining therefrom a local start time t.sub.0 i and for generating therefrom a local timestamp signal LTSSi, where the local timestamp signal LTSSi is representative of a number of time intervals having a length substantially equal to the period T.sub.mc occurring after the local start time t.sub.0 i. The ith test instrument also stores one or more local trigger values and generates one or more local trigger signals LTGSi when the local timestamp signal LTSSi equals one or more of the local trigger values.

Test system including a local trigger signal generator for each of a

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Ashland, MA, United States of America

Eric H Rosenfeld