Soitec

Commissariat a L'energie Atomique Et Aux Energies Alternatives

S.o.i.tec Silicon on Insulator Technologies

S.o.i. Tec Silicon on Insulator Technologies, S.a.

Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V.

Commissariat À L'énergie Atomique Et Aux Énergies Alternatives

Eric Guiot

Didier Landru

Oleg Kononchuk

Rainer Klaus Krause

Frank Dimroth

Christelle Veytizou

Thibaut Maurice

Eric Mazaleyrat

Fabrice Gritti

Christophe Maleville

Ionut Radu

Cécile Aulnette

Thomas Signamarcheix

Fabrice Lallement

Hugo Biard

Cecile Aulnette

Emmanuelle Lagoutte

Charlotte Drazek

Phuong Nguyen

A method for producing a substrate for the epitaxial growth of a gallium-based III-N alloy layer comprises the following successive steps: —providing a donor substrate of single-crystal silicon carbide; —implanting ions in the donor substrate to form an embrittlement zone defining a thin film layer of single-crystal SiC; —bonding the donor substrate onto a first receiving substrate via a bonding layer; —detaching the donor substrate along the embrittlement zone to transfer the thin film of SiC onto the first receiving substrate; —epitaxially growing a layer of semi-insulating SiC having a thickness greater than 1 μm on the thin film of SiC; —bonding the layer of semi-insulating SiC onto a second receiving substrate having a high electrical resistivity; —removing at least a portion of the bonding layer to detach the first receiving substrate; and —removing the transferred thin film of single-crystal SiC, to expose the semi-insulating SiC layer.

Method for producing a substrate for the epitaxial growth of a layer of a galium-based III-N alloy

A method of producing a composite structure comprising a thin layer of monocrystalline silicon carbide arranged on a carrier substrate of silicon carbide comprises: a) a step of provision of an initial substrate of monocrystalline silicon carbide, b) a step of epitaxial growth of a donor layer of monocrystalline silicon carbide on the initial substrate, to form a donor substrate, c) a step of ion implantation of light species into the donor layer, to form a buried brittle plane delimiting the thin layer, d) a step of formation of a carrier substrate of silicon carbide on the free surface of the donor layer, comprising a deposition at a temperature of between 400° C. and 1100° C., e) a step of separation along the buried brittle plane, to form the composite structure and the remainder of the donor substrate, and f) a step of chemical-mechanical treatment(s) of the composite structure.

Method for producing a composite structure comprising a thin layer of monocrystalline sic on a carrier substrate of polycrystalline SiC

An engineered substrate comprising: a seed layer made of a first semiconductor material for growth of a solar cell; a first bonding layer on the seed layer; a support substrate made of a second semiconductor material; a second bonding layer on a first side of the support substrate; a bonding interface between the first and second bonding layers; the first and second bonding layers each made of metallic material; wherein doping concentration and thickness of the engineered substrate, in particular, of the seed layer, the support substrate, and both the first and second bonding layers, are selected such that the absorption of the seed layer is less than 20%, preferably less than 10%, as well as total area-normalized series resistance of the engineered substrate is less than 10 mOhm&#xb7;cm, preferably less than 5 mOhm&#xb7;cm.

Engineered substrate with embedded mirror

This disclosure relates to a solar cell assembly structure for supporting a concentrator photovoltaic cell comprising a semiconducting structure and a diode, wherein the semiconducting structure comprises a first semiconducting region at least a part of which for placing the concentrator photovoltaic cell structure, and a second semiconducting region for realizing the diode within or on the second semiconducting region and wherein the part of the first semiconducting region for placing the concentrator photovoltaic cell structure and the second semiconducting region are not vertically overlapping.

Advanced CPV solar cell assembly process

This disclosure is related to a manufacturing method for a plurality of photovoltaic cells comprising the steps of: obtaining a plurality of photovoltaic cells placed at a first distance from each other; attaching a stretching material to the plurality of photovoltaic cells; and stretching the stretching material such that the plurality of photovoltaic cells result at a second distance from each other, wherein the second distance is greater that the first distance.

Multiple transfer assembly process

A process for avoiding formation of an Si&#x2014;SiO&#x2014;Henvironment during a dissolution treatment of a semiconductor-on-insulator structure that includes a carrier substrate, an oxide layer, a thin layer of a semiconductor material and a peripheral ring in which the oxide layer is exposed. This process includes encapsulating at least the exposed oxide layer of the peripheral ring with semiconductor material by performing a creep thermal treatment; and performing an oxide dissolution treatment to reduce part of the thickness of the oxide layer. In this process, the semiconductor material that encapsulates the oxide layer has a thickness before the oxide dissolution that is at least twice that of the oxide that is to be dissolved, thus avoiding formation of an Si&#x2014;SiO&#x2014;Henvironment on the peripheral ring where the oxide layer would otherwise be exposed.

Process to dissolve the oxide layer in the peripheral ring of a structure of semiconductor-on-insulator type

A process for fabricating a substrate that includes a buried oxide layer for the production of electronic components or the like. The process includes depositing an oxide layer or a nitride layer on either of a donor or receiver substrate, and bringing the donor and receiver substrates into contact; conducting at least a first heat treatment of the oxide or nitride layer before bonding the substrates, and conducting a second heat treatment of the fabricated substrate of the receiver substrate, the oxide layer and all or part of the donor substrate at a temperature equal to or higher than the temperature applied in the first heat treatment. Substrates that have an oxide or nitride layer deposited thereon wherein the oxide or nitride layer is degassed and has a refractive index smaller than the refractive index of an oxide or nitride layer of the same composition formed by thermal growth.

Process for fabricating a substrate comprising a deposited buried oxide layer

A process for treating a semiconductor-on-insulator type structure that includes, successively, a support substrate, an oxide layer and a thin semiconductor layer. The process includes formation of a silicon nitride or silicon oxynitride mask on the thin semiconductor layer to define exposed areas at the surface of the layer which are not covered by the mask, and which are arranged in a desired pattern; and application of a heat treatment in a neutral or controlled reducing atmosphere and under controlled conditions of temperature and time to induce at least a portion of the oxygen of the oxide layer to diffuse through the thin semiconductor layer, thereby resulting in the controlled reduction in the oxide thickness in the areas of the oxide layer corresponding to the desired pattern. The mask is formed so as to be at least partially buried in the thickness of the thin semiconductor layer.

Process for locally dissolving the oxide layer in a semiconductor-on-insulator type structure

The invention relates to a method for manufacturing a compound material wafer. The technique includes forming a weakened zone in a source substrate, attaching the source substrate to a handle substrate to form a source-handle assembly, and thermally annealing the source-handle assembly to further weaken the weakened zone. The method also includes holding the assembly at a holding temperature, and detaching the source substrate from the assembly at the weakened zone at the holding temperature. The holding temperature is greater than room temperature but does not promote further weakening of the weakened zone.

Method for manufacturing a compound material wafer

The invention relates to a method for manufacturing a material compound wafer by forming a predetermined splitting area in a source substrate; attaching the source substrate to a handle substrate to form an assembly; heating the assembly for weakening the predetermined splitting area; and determining a degree of weakening of the predetermined splitting area which evidences the physical strength of the predetermined splitting area during or after heating to detect anomalies that may lead to damage of the source substrate, handle or assembly. The degree of weakening is advantageously determined in-situ and may be determined continuously or periodically during the heating. The invention further relates to an apparatus for thermal annealing device used in the manufacturing process of a material compound wafer. This apparatus generally includes a device for thermally annealing the assembly described above; and a device for determining the degree of weakening of the predetermined splitting area during or after thermal annealing to detect anomalies that may lead to damage of the source substrate, handle or assembly.

Growing community of inventors

Goncelin, France

Eric Guiot