International Business Machines Corporation

Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Eric Gouze

Frederic Bottausci

Pascal Mailley

Olivier Fuchs

Robert M Hornung

Ieng Ong

Martine Bonneau

Jean-Marc Piccino

Frédéric Bottausci

An electrochemical measurement cartridge includes a container including a first analysis chamber for receiving a fluid to be analyzed and a second calibration chamber for receiving a calibration fluid; an electrochemical measurement sensor including at least one work electrode and one reference electrode; a container supporting the sensor and a cover arranged mobile relative to one another to confer on the cartridge at least two separate operating configurations, a first configuration in which the sensor is communicating with the first analysis chamber and a second configuration in which the sensor is communicating with the second calibration chamber; sealing between the chambers of the container and the cover; and a drive member for providing a relative movement of the container relative to the cover.

Electrochemical measurement cartridge

A CMOS FET master slice integrated circuit (20) of the gate-array type implemented in a semiconductor logic chip, comprises a plurality of core cells (CELL1, CELL2, . . . ) arranged adjacent one another on a repetitive basis in a row direction to form horizontal stripe shaped functional gate region (21) of a determined height (H). Each core cell (e.g., CELL1) is comprised of four different sized devices: one small and one large NFET (N1.1, N2.1), thus one small and one larger PFET (P1.1, P2.1), that are disposed in a column direction. The NFETs have separate gate electrodes (GN1.1, GN2.1) to define individual devices, while the PFETs have preferably a common gate electrode (GP1) to define a single device. The relative size of NFETs and PFETs have been optimized to provide the required functionality to the latches and to ensure the balanced rise and fall delays in a maximum of basic logic circuits of the chip. As a result, the use of such core cells, allows that complex logic functions, such as latches, can be implemented in gate arrays that have a density and performance comparable with standard cell circuits. In addition, the use of these core cells also permits optimization of other basic logic circuits (INV, NOR, . . . ) that are used in critical logic paths and clock distribution trees, where balanced delays are highly desirable.

Gate array cell having FETs of different and optimized sizes

Growing community of inventors

Grenoble, France

Eric Gouze