International Business Machines Corporation

Sony Corporation

Adeia Semiconductor Bonding Technologies Inc.

Eric Gerhard Liniger

Robert F Cook

Son Van Nguyen

Ronald Lee Mendelson

Thomas M Shaw

Michael Wayne Lane

Donald W Brouillette

Kangguo Cheng

Juntao Li

Tenko Yamashita

Chanro Park

Sanjay C Mehta

Thomas J Haigh, Jr

Stephen McConnell Gates

Griselda Bonilla

Wayne John Howell

Thomas George Ference

Chih-Chao Yang

James L Hedrick

Robert Dennis Miller

Xiao Hu Liu

Craig Jon Hawker

Willi Volksen

Howard Smith Landis

Hormazdyar M Dalal

James Patrick Doyle

Stephen Peter Ayotte

Darryl D Restaino

Hazara Singh Rathore

Stephan Alan Cohen

Kenneth Raymond Carter

Du Binh Nguyen

Birendra N Agarwala

Brett H Engel

Do Yeung Yoon

Sarah L Lane

John M Blondin

Kensaku Ida

Chunyan E Tian

Diana Llera-Hurlburt

Travis S Longenbach

Xio Hu Liu

Martha Alyne Harbison

Richard W Procter

David Frederick Diefenderfer

Alfred Grill

Elbert Emin Huang

Sandra Guy Malhotra

Gareth Geoffrey Hougham

John Anthony Fitzsimmons

Robert J Von Gutfeld

Christos Dimitrios Dimitrakopoulos

Deborah A Neumayer

Stephen Mark Rossnagel

Jeffrey Curtis Hedrick

David L Questad

Kang-Wook Lee

Chao-Kun Hu

Roy Arthur Carruthers

Victor Yee-Way Lee

William Francis Landers

Lynne Marie Gignac

John Bruley

James Henry Glownia

Stephen Alan Cohen

Eva Erika Simonyi

Pak Leung

John C Hay, Jr

Andrew Robert Eckert

Richard Charles Whiteside

Dean R Sanders

Sung-Mog Kim

Semiconductor devices having air gap spacers that are formed as part of BEOL or MOL layers of the semiconductor devices are provided, as well as methods for fabricating such air gap spacers. For example, a method comprises forming a first metallic structure and a second metallic structure on a substrate, wherein the first and second metallic structures are disposed adjacent to each other with insulating material disposed between the first and second metallic structures. The insulating material is etched to form a space between the first and second metallic structures. A layer of dielectric material is deposited over the first and second metallic structures using a pinch-off deposition process to form an air gap in the space between the first and second metallic structures, wherein a portion of the air gap extends above an upper surface of at least one of the first metallic structure and the second metallic structure.

Air gap spacer formation for nano-scale semiconductor devices

A method for predicting the electrical functionality of a semiconductor package, the method includes performing a first stiffness test for a first semiconductor package, receiving failure data for the first semiconductor package, the failure data includes results of an electrical test performed after the first semiconductor package is assembled on a printed circuit board, generating a database comprising results of the first stiffness test as a function of the failure data for the first semiconductor package, performing a second stiffness test for a second semiconductor package, identifying a unique result from the results of the first stiffness test in the database, the unique result aligns with a result of the second stiffness test, and predicting a failure data for the second semiconductor package based on the failure data for the first semiconductor package which corresponds to the unique result of the first stiffness test identified in the database.

Predicting semiconductor package warpage

An interconnect structure includes a first dielectric material having an undercut region located at an upper surface thereof. A first conductive structure is located above a first area of the undercut region. The first conductive structure comprises a first conductive metal portion having a diffusion barrier portion located on one sidewall surface of the first conductive metal portion and having a metal liner located on another sidewall surface and a bottom surface of the first conductive metal portion. A second conductive structure is located above a second area of the undercut region. The second conductive structure comprises a second conductive material portion having a diffusion barrier portion located on one sidewall surface of the second conductive material portion and having a metal liner located on another sidewall surface and a bottom surface of the second conductive metal portion. A gap is located between the first and second conductive structures.

Nanoscale interconnect structure

A method of annealing a semiconductor and a semiconductor. The method of annealing including heating the semiconductor to a first temperature for a first period of time sufficient to remove physically-adsorbed water from the semiconductor and heating the semiconductor to a second temperature, the second temperature being greater than the first temperature, for a period of time sufficient to remove chemically-adsorbed water from the semiconductor. A semiconductor device including a plurality of metal conductors, and a dielectric including regions separating the plurality of metal conductors, the regions including an upper interface and a lower bulk region, the upper interface having a density greater than a density of the lower bulk region.

Multiple step anneal method and semiconductor formed by multiple step anneal

A low k dielectric stack having an effective dielectric constant k, of about 3.0 or less, in which the mechanical properties of the stack are improved by introducing at least one nanolayer into the dielectric stack. The improvement in mechanical properties is achieved without significantly increasing the dielectric constant of the films within the stack and without the need of subjecting the inventive dielectric stack to any post treatment steps. Specifically, the present invention provides a low k dielectric stack that comprises at least one low k dielectric material and at least one nanolayer present within the at least one low k dielectric material.

Low k dielectric CVD film formation process with in-situ imbedded nanolayers to improve mechanical properties

The present invention provides a method of strengthening a structure, to heal the imperfection of the structure, to reinforce the structure, and thus strengthening the dielectric without compromising the desirable low dielectric constant of the structure. The inventive method includes the steps of providing a semiconductor structure having at least one interconnect structure; dicing the interconnect structure; applying at least one infiltrant into the interconnect structure; and infiltrating the infiltrant to infiltrate into the interconnect structure.

Strengthening of a structure by infiltration

The present invention relates to a process for preparing a robust crack-absorbing integrated circuit chip comprising a crack trapping structure containing two metal plates and a via-bar structure sandwiched between said plates.

Crack trapping and arrest in thin film structures

A method is disclosed of repairing wire bond damage on semiconductor chips such as high speed semiconductor microprocessors, application specific integrated circuits (ASICs), and other high speed integrated circuit devices, particularly devices using low-K dielectric materials. The method involves surface modification using reactive liquids. In a preferred embodiment, the method comprises applying a silicon-containing liquid reagent precursor such as TEOS to the surface of the chip and allowing the liquid reagent to react with moisture to form a solid dielectric plug or film () to produce a barrier against moisture ingress, thereby enhancing the temperature/humidity/bias (THB) performance of such semiconductor devices.

Method and structure to enhance temperature/humidity/bias performance of semiconductor devices by surface modification

Method of forming crack trapping and arrest in thin film structures

A method for forming a ultralow dielectric constant layer with controlled biaxial stress is described incorporating the steps of forming a layer containing Si, C, O and H by one of PECVD and spin-on coating and curing the film in an environment containing very low concentrations of oxygen and water each less than 10 ppm. A material is also described by using the method with a dielectric constant of not more than 2.8. The invention overcomes the problem of forming films with low biaxial stress less than 46 MPa.

Ultralow dielectric constant layer with controlled biaxial stress

Growing community of inventors

Sandy Hook, CT, United States of America

Eric Gerhard Liniger