Hewlett-packard Company

Eric G Tausheck

Thomas A Keaveny

Joe H Steinmetz

A system which performs chained direct memory access (DMA) operations, includes a working set of buffers, a first-in-first-out memory, a first DMA co-processor, a second DMA co-processor and a controlling processor. The working set of buffers are available for receiving data from chained DMA operations. The first-in-first-out memory store addresses of buffers, from the working set of buffers, which are available for immediate allocation. The first DMA co-processor and the second DMA co-processor perform the chained DMA operations. The controlling processor sets up the chained DMA operations and adds addresses of free buffers to the first-in-first-out memory. When performing a first chained DMA operation, the first DMA co-processor accesses the first-in-first-out memory to allocate for itself a first buffer from the queue of buffers when a first link in the first chained DMA operation requires a buffer. When the first buffer is filled, the first DMA co-processor immediately notifies the controlling processor. When performing a second chained DMA operation, the second DMA co-processor accesses the first-in-first-out memory to allocate for itself a second buffer from the queue of buffers when a first link in the second chained DMA operation requires a buffer. When the second buffer is filled, the second DMA co-processor immediately notifies the controlling processor.

Dynamic allocation and reallocation of buffers in links of chained DMA

A network bridge includes a processor, a common memory, a first interface to a first network and a second interface to a second network. Upon the first interface receiving a first request to transfer data from a device on the first network, the processor seeds a portion of a first buffer within the first common memory with a predetermined polling pattern. The processor polls the portion of the first buffer to determine when data has arrived into the first buffer. When the processor determines that data has arrived into the first buffer, the processor authorizes the second interface to set up a write process with a device on the second network.

Low latency bridging between high speed bus networks

A high-performance network/bus multiplexer that exchanges data transfer commands and data between different communications mediums, such as the Fibre Channel and one or more SCSI buses. High-performance is achieved by avoiding transmitting read bus operations through bus bridges, and by limiting contention for buses by connecting Fibre Channel host adapters to a first internal bus and SCSI adapters to a second internal bus.

Architecture for a high-performance network/bus multiplexer

A co-processor works in conjunction with a primary processor which does not natively support co-processing. In a memory which provides instructions for the primary processor, parameters for use by the co-processor are embedded within the instructions. This is done by placing the parameters in fields which are unused by the primary processor. When the primary processor accesses the local memory, the addresses generated by the primary processor are monitored by the co-processor. When the co-processor detects a pre-determined combination within an address generated by the primary processor, the co-processor accesses the data sent from the local memory to the primary processor. The co-processor then extracts the parameters embedded within the unused fields of the accessed data.

Co-processor monitoring address generated by host processor to obtain

Entries for data transactions are stored in and accessed from a nexus table. Data transactions over a bus are identified using a first reference. Further, data transactions may be additionally identified using a second reference. When a data transaction is identified only by a first reference, an entry for the data transaction is stored in a location within a first portion of the nexus table. Entries in the first portion of the nexus table are indexed using the first reference for the data transaction. When a data transaction is identified using both a first reference and a second reference, an entry for the data transaction is stored in a location within a second portion of the nexus table. Entries in the second portion of the nexus table are indexed using the second reference number for the data transaction. The first reference is not used in indexing entries in the second portion of the nexus table.

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Citrus Heights, CA, United States of America

Eric G Tausheck