Texas Instruments Corporation

The Texas A&m University System

Eric G Soenen

Gregory B Davis

Ching-Yuh Tsay

Thomas F Adkins

Andrew Marshall

James Robert Todd

Joe R Trogolo

Henry T Yung

Russell K MacDonald

Abdellatif Bellaouar

Roman Staszewski

Kirk D Peterson

Maher Mahmoud Sarraj

James E Nave

Mounir Fares

Irfan Azam Chaudhry

Karthikeyan Soundarapandian

Randall L Geiger

T Lakshmi Viswanathan

Arash Loloee

Steve Martindell

Andrew J Cringean

Angela C Dycus

Loulis J Izzi

Michiel deWit

Angie Dycus

James R Craig

A correlated double sampled/programmable gain amplifier (CDS/PGA) is disclosed which is operable to precondition a CCD output analog signal. The CDS/PGA includes an operational amplifier that is configured in a sample hold operation. The single-ended input is first clamped by a switch ( ) to clamp the DC level therein for a given pixel. A switch ( ) then samples the reset level onto a sampling capacitor ( ), and a switch ( ) thereafter samples the video signal onto one plate of a capacitor ( ). The lower plates of the capacitors ( ) and ( ) are then equalized and the other plates thereof connected to the positive and negative inputs of the operational amplifier ( ). An offset is provided by a programmable DAC ( ) to account for the dark current offset. The output scale is adjusted or mapped by limiting the output between a negative and a positive reference input. The sampling capacitors ( ) and ( ) can be varied to vary the gain of the amplifier.

Complete CDS/PGA sample and hold amplifier

A pipelined data converter current biasing system employs a frequency-to-voltage converter (FVC) operational to convert a plurality of desired sampling frequencies to a plurality of output voltages and a voltage-to-current (V to I) converter operational to convert the plurality of output voltages to a plurality of bias currents. The plurality of bias currents function to bias the data converter operational amplifiers such that the data converter power consumption is dependent on the plurality of sampling frequencies in a way that optimizes power consumed by the data converter with respect to the sampling frequency.

System and method for optimizing power in pipelined data converters

A pipelined analog-to-digital converter system ( ) is responsive to an analog input signal ( ). The system includes four pipeline stages ( ), which each produce a respective digital output ( ) that is coupled to a combining circuit ( ). The combining circuit generates the digital output ( ) of the system. Each pipeline stage includes an analog-to-digital converter ( ), which generates the digital output for that stage. A shuffler circuit ( ) randomly shuffles the bits of this digital output, in order to generate shuffled switching signals, which in turn are used to control electronic switches ( ) associated with several capacitors (C1-C4). By randomly shuffling the switching signals, the effects caused by variation of any capacitor from an ideal value are randomized. This avoids nonlinearity such as harmonic distortion in the analog output signal ( ) from that stage.

Method and apparatus for obtaining linearity in a pipelined analog-to-digital converter

A skewless differential switching circuit uses skewless switching elements to convert complementary signals with skew into complementary output signals with minimal time skew between the output signals and with equalized rise and fall times of the output signals for minimum harmonic distortion.

Skewless differential switching scheme for current-mode digital-to-analog converters

A trimming circuit for a gain stage in a pipeline analog-to-digital converter includes an amplification stage (30) having associated therewith on one input thereof a coupling capacitor (38). In parallel with the coupling capacitor is provided a trimming network. The trimming network includes a series configuration of a coupling capacitor and a plurality of trimming capacitors, which trimming capacitors can be disposed in parallel with each other. Each of the trimming capacitors has associated therewith a switch which allows them to be selectively disposed in series with a coupling capacitor (42) and in parallel with each other. This trimming network is connected in parallel with the sampling capacitor (38). The input to the amplifier is isolated from the trimming network with a buffer (62) which is operable to isolate the impedance of the trimming capacitors from the input and from preceding stages.

Trimming circuitry for pipeline A/D converter

A trimming algorithm for a pipeline A/D converter includes the step of trimming the input sampling capacitor on each of the gain stages for each stage of the pipeline A/D converter. The input thereof is swept from a minimum to a maximum analog voltage and then the integral non-linearity (INL) of the A/D converter determined. The maximum transitions are then examined to determine which transitions are associated with which stage. The transitions for a given stage then constitute the gain error for these stages. The trim values are determined from this gain error and then the trim values incorporated into each of the gain stages.

Trimming algorithm for pipeline A/D converter using integrated

An integrated circuit (IC) configurable as transmitter/receiver includes a method of preventing unauthorized learning and reproduction of an access code as a security measure. When the IC is configured as a receiver and placed in the learn mode, a flag is set in a memory of a microcontroller. If later configured as a transmitter, the microcontroller checks the flag upon power up and if the flag is set, the stored code is randomized so transmission of it is impossible.

Method of preventing unauthorized reproduction of a transmission code

A pipelined analog-to-digital converter is disclosed having a plurality of sample and hold converter stages, each having an interstage amplifier (28) associated therewith. This is a differential amplifier that is implemented without common-mode feedback. The sample and hold stage operates on a reset phase and a gain/DAC phase, wherein the output of the reconstructive DAC is summed with the input to the amplifier (28). A differential input amplifier (60) has the inputs thereof set to common-mode input voltage with a feedback capacitor biased to a common-mode output bias point. During the gain/DAC phase, the bias input is removed and the feedback capacitor connected across the input/output of the amplifier (60). This effectively establishes the common-mode bias points for use by the amplifier (60) during the gain/DAC phase. Further, the differential inputs of the amplifier (60) are connected to one side of respective sampling capacitors, the other side thereof connected through a respective switch to the differential inputs. During the reset phase the input voltage is sampled onto the capacitors and, during the gain/DAC phase, the gates of the capacitors are connected together to remove any common-mode voltage from the input prior to being input to the amplifier (60).

Method and apparatus for implementing a pipelined A/D converter with

A computer implemented method transmits and receives an information signal. A common start position is established for the receive mode where the information signal is received and a transmit mode where the information signal is transmitted. Either the receive mode to receive the information signal or the transmit mode to transmit the information signal is entered subsequent to establishing the common position. The start position is returned to after the receive mode the transmit the learn mode and the self-test mode has been entered.

Decryption and encryption transmitter/receiver with self-test, learn and

A random number generator includes a plurality of fully differential amplifiers (30) configured as a ring oscillator (22). The output of the ring oscillator (22) is input to a comparator/latch circuit (32) for determining the zero crossing for the ring oscillator. The ring oscillator is a self-oscillating structure that has an oscillation frequency with jitter superimposed thereon. This jitter is a result of the internal thermal noise associated with the integrated circuits that are utilized to realize the amplifiers (30). Each of the amplifiers (30) that make up the ring oscillator operate on a substantially constant current and are subsequently isolated from changes in the power supply. As such, the variations in the frequency thereof are caused solely by thermal noise. The comparator/latch circuit (32) is operable to compare the difference on the output of the last stage of the ring oscillator (22) and the output of the comparator/latch (32) is then sampled by a CPU (12) that is operated on a separate master clock (18). This allows the master clock (18), upon which the sample operation is based, to be completely separate from the ring oscillator (22).

Random binary number generator

An integrated analog to digital interface subsystem for imaging applications includes digital global and digital pixel by pixel offset correction and scaling. The integrated interface 2 includes 3 DAC's 2c1-2c3 that are used to do a rough offset cancellation on the three analog input signals (RGB) in the analog domain. A triple sample/hold circuit 2a samples the RGB signals simultaneously, multiplexes the data and passes the three signals on the ADC 2b sequentially (at about 3 times the data rate). The sample/hold circuit 2a has the capability to operate in fully differential as well as single ended input mode, and can perform correlated double sampling if needed. A high resolution ADC 2b converts the 3 multiplexed signals from simple/hold circuit 2a. A first digital offset correction circuit 2f restores the level of the RGB signals in the digital domain on a pixel by pixel basis. A first digital gain correction circuit 2g compensates for sensitivity variations of the RGB sensors in the digital domain on a pixel by pixel basis. A second digital offset correction circuit 2h restores the overall DC level of the RGB signals in the digital domain. A second digital gain correction circuit 2i compensates for overall sensitivity variations of the RGB sensors in the digital domain. A serial interface 2d is used to load the overall gain and offset coefficients.

Analog to digital video converter

An integrated circuit configurable as a transmitter/receiver includes learn capabilities that allows a receiver IC to memorize the identification pattern of a specific transmitter.

Combined transmitter/receiver integrated circuit with learn mode

A System and method for calibrating a chip after packaging including providing a packaged chip, providing programmable non-volatile storage having a plurality of non-volatile storage elements in the chip and providing a volatile storage having a plurality of volatile storage elements in the chip with one volatile storage element associated with one non-volatile storage element. The chip includes circuitry responsive to a predetermined signal to permit the non-volatile storage to be programmed in accordance with data stored in the volatile storage and to a predetermined signal to prevent external alteration of the non-volatile storage. The non-volatile storage is preferably a plurality of fuses. The volatile storage is preferably a shift register. The circuitry in the chip includes a bistable device responsive to the predetermined signal to assume a first condition to permit the non-volatile storage to be programmed and responsive to the alteration of the predetermined signal to assume a second condition which does not allow alteration of data. The system further includes a non-volatile storage element settable to one of a first or a second condition and preset to the first condition, the circuitry in the chip responsive to the first condition to permit the non-volatile storage to be programmed in accordance with data stored in the storage and responsive to the second condition to prevent external alteration of the non-volatile storage. The condition of the non-volatile element determines whether or not the first state (program) of the bistable device can be entered.

Method for programming permanent calibration information at final test

An integrated circuit (IC) configurable as transmitter/receiver includes a microcontroller to aid in decoding a pulse width modulated serial dam stream. The microcontroller accomplishes the decoding with the aid of a counter and an external clock signal without the necessity of using interrupts. Edge detection circuitry detects the rising and the rising edge of the incoming data pulse. The external clock signal clocks a counter to determine how many clock signals the incoming pulse corresponds to. The microcontroller polls the counter on the rising edge and the falling edge.

Apparatus and method to decode a pulse width modulated serial data stream

A remote control access system uses a transmitter and a receiver. The transmitter generates an encrypted identification code which the receiver decrypts and grants access to the system if the decrypted code matches an identification code stored in the receiver. The encryption occurs by taking a 40 bit identification code and forming 5 bytes (8 bytes each). The 5 bytes are logic exclusive OR'd to form a 5 byte wide encrypted code. Decryption occurs by performing the opposite exclusive OR operation on the 5 byte wide encrypted code to convert it back to the 5 byte identification code. The 4 most significant bytes of the decrypted code are compared against the 4 most significant bytes of the previous stored decrypted code in the receiver. If the comparison yields a zero, this means the least significant byte will be within 2.sup.8 or 256 of each other and access will be granted.

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Plano, TX, United States of America

Eric G Soenen