Alcatel Lucent

Eric Fortin

David Martin Harvey

Hayrettin Buyuktepe

Michael Ah-kee

A method and apparatus are provided for facilitating access from a control system to the memory of a processor across two buses, one of which acts as a bottleneck to communication between the control system and the processor. A bridge between the two buses acts as an intermediary. The control system issues simple diagnosis and data loading verification commands across a slow bus to the bridge. The bridge then performs the data intensive tasks by communicating with the processor through a faster bus. The bridge writes and reads data to the processor, and generates checksums of the written and read data. The bridge then returns status information to the control system indicative of the comparison of the checksums. In the case of memory diagnosis, the control system need only issue a simple command to the bridge through the slower, which then diagnoses the memory through the fast bus by writing and reading data, and returns a status to the control system through the slow bus. In the case of verification of loading of data, the bridge generates a checksum of the written data and then generates of a checksum of the data it reads back from the processor through the fast bus, and returns a status to the control system through the slow bus.

Memory access assist

The backpressure mechanism and method described here do not completely shut off the traffic when a queue is experiencing congestion. Instead of completely shutting off the traffic and waiting for the effects, a series of backpressure pulses are sent to the upstream stage for intermittently slowing the traffic between the upstream and downstream stages. These pulses of backpressure effectively slowly down the rate of the ingress traffic to the queue to a rate less than the egress rate. This allows queue utilization to slowly decrease. These pulses continue as long as the queue utilization is above a threshold called 'Starving Threshold'. This technique allows much lower queue utilization, thus requiring smaller queues sizes.

Pulsed backpressure mechanism for reduced FIFO utilization

A method for synchronizing a data signal to a clock signal in a source-synchronous system, the source-synchronous system having first and second systems linked by an interface, the first system providing the clock signal to the second system, the second system providing the data signal and a return clock signal synchronous to the data signal to the first system, the method comprising: determining a first time delay between the clock signal and the return clock signal and delaying the data signal by the first time delay; after a predetermined period, determining a second time delay between the clock signal and the return clock signal; determining a difference between the first and second time delays; and, further delaying the data signal by at least a portion of the difference to thereby compensate for a temperature change of the source-synchronous system.

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Nepean, Canada

Eric Fortin