Sun Microsystems, Inc.

Eric Eugene Graf

Daniel P Drogichen

Douglas B Meyer

Andrew E Phelps

James Anthony Gilbert

Steven Fitzgerald Weiss

Patricia Shanahan

Donald Kane

Don Kane

The present invention provides a method and apparatus for updating serial devices. The apparatus includes a plurality of serial registers. The apparatus further includes a device adapted to provide a signal and a plurality of parallel registers, wherein each of the parallel registers is adapted to access at least one of the plurality of serial registers at substantially the same time in response to detecting the signal.

Method and apparatus for updating serial devices

A method and apparatus for abandoning an interrupted task is provided. The method includes setting at least one of a plurality of logic elements associated with at least one of a plurality of first registers, wherein the plurality of first registers are adapted to access data stored in a plurality of second registers at substantially the same time when the plurality of logic elements are set. The method further includes resetting the plurality of logic elements substantially before the plurality of first registers access the data stored in the plurality of second registers.

Method and apparatus for abandoning an interrupted task

A method and apparatus for providing error isolation in a multi-domain computer system. The system includes a plurality of system resources allocated to form at least a first and second domain. The system resources of the first domain perform a set of transactions independent from a set of transactions performed by the system resources of the second domain. The system further comprises at least one interface for coupling one system resource from the first domain and one system resource from the second domain. The at least one interface tracks the set of transactions performed by the one system resource of the first domain and the one system resource of the second domain independently from one another.

Method and apparatus for providing error isolation in a multi-domain computer system

A multiprocessor system is disclosed that employs an apparatus and method for caging a redundant component to allow testing of the redundant component without interfering with normal system operation. In one embodiment the multiprocessor system includes at least two system controllers and a set of processing nodes interconnected by a network. The system controllers allocate and configure system resources, and the processing nodes each include a node interface that couple the nodes to the system controllers. The node interfaces can be individually and separately configured in a caged mode and an uncaged mode. In the uncaged mode, the node interface communicates information from either of the system controllers to other components in the processing node. In the caged mode, the node interface censors information from at least one of the system controllers. When all node interfaces censor information from a common system controller, this system controller is effectively &ldquo;caged&rdquo; and communications from this system controller are thereby prevented from reaching other node components. This allows the caged system controller along with all its associated interconnections to be tested without interfering with normal operation of the system. Normal system configuration tasks are handled by the uncaged system controller. The uncaged system controller can instruct the node interfaces to uncage the caged system controller if the tests are successfully completed.

Diagnostic cage for testing redundant system controllers

A multiprocessing computer system provides the hardware support to properly test an I/O board while the system is running user application programs and while preventing a faulty board from causing a system crash. The system includes a centerplane that mounts multiple expander boards. Each expander board in turn connects a microprocessor board and an I/O board to the centerplane. Prior to testing, the replacement I/O board becomes a part of a dynamic system domain software partition after it has been inserted into an expander board of the multiprocessing computer system. Testing an I/O board involves executing a process using a microprocessor and memory on a microprocessor board to perform hardware tests on the I/O board. An error cage, address transaction cage, and interrupt transaction cage isolate any errors generated while the I/O board is being tested. The error cage isolates correction code errors, parity errors, protocol errors, timeout errors, and other similar errors generated by the I/O board under test. The address transaction cage isolates out of range memory addresses from the I/O board under test. The interrupt transaction cage isolates interrupt requests to an incorrect target port generated by the I/O board under test. The errors generated by the I/O board are logged in a status register and suppressed.

Cage for dynamic attach testing of I/O boards

A multiprocessor system is disclosed that employs an apparatus and method for caging a redundant component to allow testing of the redundant component without interfering with normal system operation. In one embodiment the multiprocessor system includes at least two system controllers and a set of processing nodes interconnected by a network. The system controllers allocate and configure system resources, and the processing nodes each include a node interface that couple the nodes to the system controllers. The node interfaces can be individually and separately configured in a caged mode and an uncaged mode. In the uncaged mode, the node interface communicates information from either of the system controllers to other components in the processing node. In the caged mode, the node interface censors information from at least one of the system controllers.

Growing community of inventors

Hillsboro, OR, United States of America

Eric Eugene Graf