International Business Machines Corporation

Cadence Design Systems, Inc.

Eric Ernest Millham

Scott Whitney Gould

Steven Paul Hartman

Christine Marie Fuller

Joseph Andrew Iadanza

Frank Ray Keyser, Iii

Terrance John Zittritsch

Brian A Worth

Kim P Clinton

Allan Robert Bertolet

Timothy Shawn Reny

Gulson Yasar

Adolf E Wirsing

Kenneth Ferguson

Gulsun Yasar

Stuart E Greer

Ronald Raymond Palmer

A programmable logic cell has four cell input nodes and a plurality of combinational logic circuits. Four inverter circuits are provided for programmably inverting respective input logic signals, each inverter circuit having an inverter input node connected to a respective cell input node for accepting its respective input logic signal therefrom. Each inverter is programmable into a first state wherein a logic signal representing the complement of the input logic signal is provided to the inverter output node, and a second state wherein a logic signal representing the non-complement of the input logic signal is provided to the inverter output node. The inverter circuits buffer their input logic signals in both their first and second states. A first logic gate of the plurality of combinational logic circuits has first and second inputs each connected to a respective output node of one of two of the four inverter circuits, and a second logic gate has first and second inputs each connected to a respective output node of one of the other two of the four inverter circuits. The inverter circuits may be implemented as XNOR gates.

Programmable inverter circuit used in a programmable logic cell

In a Field Programmable Gate Array ('FPGA') design system, a configuration is generated. A path of the configuration is selected as a critical path for optimization. The critical path is optimized by rerouting connections between the logical primitives of the critical path. Prior to the rerouting, the logical primitives of the critical path may be optimally placed within the FPGA configuration. Optimal performance of the critical path is thus achieved.

Method and system for optimizing a critical path in a field programmable

A computer implemented method for the automated placement and routing in the design of field programmable gate arrays achieves optimal timing. In a library of primitives and macros from which a designer may choose to implement a given circuit design, at least some of said macros are 'semi-hard' macros where direct connections and relative placements are specified while local bus routing is requested in a manner that does not restrict macro placement. A logical netlist containing references to macros and how to connect them together to perform a logical function is first created. The logical netlist is then translated to a physical netlist using a mapper function. This physical netlist for the semi-hard macros specifies what is to be connected but not how. The best place to put each macro on the field programmable gate array is found using a placer function. The placer function thus determines an absolute position of the macros. Pre-defined macro direct connections are routed using a router function. The router function determines an optimal path to connect the semi-hard macros. Finally, a bitstream is generated from placement and routing information developed by the placer and router functions to program the field programmable gate array to perform the netlist logical function.

Field programmable gate arrays using semi-hard multicell macros

A programmable logic cell has four logic gates, two of which are configurable. The two configurable logic gates are positioned near the logic cell inputs. Each configurable logic gate has two inputs, each input being connected to one of the four logic cell inputs. The remaining two logic gates receive the outputs of the configurable logic gates. Four independent logic cell input nodes are provided, each having associated therewith a programmable input multiplexer. Each input multiplexer can have inputs connected to at least two types of interconnect conductors. The cell also has two output paths, each having associated therewith an independently-controlled output multiplexer. The output of each output multiplexer is connected to an input of the other output multiplexer. Additional features include a multiplexer having inputs connected to two cell input nodes, a select input connected to a third logic cell input node, and an output connected to a cell output node; a system low-skew data (e.g., clock) input available to at least one of the input multiplexers; a flip-flop connected within the logic cell; and internal cell feedback. The preferred method of programming utilizes user-programmed SRAM memory cells.

Programmable logic cell

A programmable array having programmable logic cells, a programmable interconnect network and a programmable I/O system. Two I/O interfaces are provided for respective logic cells about the perimeter of the array. The I/O interfaces comprise input, output and enable paths. Each of these paths has an associated multiplexer. An I/O routing network is positioned about the perimeter of the array. Conductors connecting the I/O interface multiplexers to the programmable interconnect network also intersect, and can be programmably connected to, buses of the I/O routing network.

Programmable array I/O-routing resource

Programmable logic cell having configurable gates and multiplexers

A programmable interconnection system for a programmable array includes pluralities of parallel buses for rows and columns of logic cells arranged in the array. Two groups of seven buses are provided for each row or column of logic cells. The buses include conductors connectable to each other, and selectively connectable to, or isolated from, the logic cells. A hierarchy of conductor lengths is disclosed to provide intra-sector and inter-sector bussing. Staggered switching is employed for adjacent sector access.

Programmable array interconnect network

A method and apparatus for depositing the material onto a substrate is provided. The apparatus includes a mesh member which has impregnated therein the material which is to be vapor deposited. The mesh member with the material thereon is heated to vaporize the material and the vaporized material is then deposited onto the desired substrate. Preferably the material that is deposited is maintained in a crucible having an opening and the mesh member is disposed over the opening. The material in the crucible is vaporized and condensed onto the mesh member, and the condensed material wicks through the mesh member and then revaporizes from the top of the mesh member and is deposited onto the substrates.

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St. George, VT, United States of America

Eric Ernest Millham