Bull Hn Information Systems, Inc.

Eric Earl Conway

Russell Wayne Guenthner

William A Shelly

Charles P Ryan

Boubaker Shaiek

Ron Yoder

Claude Rabel

In a Cache-Coherent Non-Uniform Memory Architecture (CC-NUMA), the time as measured in cycles that it takes for cache control signals to travel between processors ( ) sharing an L2 cache ( ) differs from the time it takes for those signals to travel between processors ( ) not sharing the same L2 cache ( ). This difference, or DELTA, is dynamically computed by computing ( ) the time it takes for a invalidate cache line cache command to travel between a local processor ( ) and a master processor ( ). This computation ( ) is then made for the time it takes the signal to travel between a remote processor ( ) and the master processor ( ). The difference ( ) is the DELTA value in cycles. This DELTA value can then be utilized to bias delay values when exhaustively testing the interactions among multiple processors in a CC-NUMA environment ( ).

Method and apparatus for determining CC-NUMA intra-processor delays

A processor ( ) in a data processing system simultaneously loads multiple registers ( ) with a single value for fast domain switching. A domain switch instruction asserts a register block write signal ( ) along with the register write signal ( ) when block writing the single value to the set of registers ( ). Register address lines ( ) are decoded in two sets: a first set of decoded address lines ( ) specifying a block of registers; and the second set ( ) specifying one register in the block of registers. When the register block write signal ( ) is asserted during a register write, the second set of decoded address lines ( ) are ignored, and all registers in the block of registers ( ) selected by the first set of decoded address lines ( ) are simultaneously loaded with a common value. Additional drive requirements are solved either by adding a buffer ( ) to each register bit, or by disabling ( ) the feedback path ( ) in each register bit during block writes.

Data processing system utilizing multiple resister loading for fast domain switching

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Mesa, AZ, United States of America

Eric Earl Conway