Honeywell International Inc.

Eric E Vogt

Cheisan J Yue

James L Tucker

Andrzej Peczalski

Paul S Fechner

Dale F Berndt

William Frank Witcraft

Gordon Alan Shaw

Gregor D Dougal

Todd N Handeland

Michael S Liu

Keith W Golke

William L Larson

Mohammed A Fathimulla

Harry H L Liu

Greg A Michaelson

Cheisen J Yue

The present disclosure describes a stacked integrated circuit system that includes two integrated circuit layers stacked on opposite sides of an interposer layer. The interposer layer may include at least one integrated circuit die and an interposer portion that includes a plurality of electrically conductive pillars arranged in a laterally patterned array within the interposer layer.

Integrated circuit stack including a patterned array of electrically conductive pillars

In some examples, a programmable electrical fuse includes at least one structural feature that increases a thermal gradient between an anode and a cathode of the programmable electrical fuse. For example, a device may include a semiconductor substrate, an electrically insulating layer overlying the semiconductor substrate, and a programmable electrical fuse overlying a portion of the electrically insulating layer. The programmable electrical fuse may include a cathode, an anode, and a conductor link connecting the cathode and the anode. The electrically insulating layer may define a first thickness between the semiconductor substrate and the cathode and a second thickness between the semiconductor substrate and the anode, and the first thickness being less than the second thickness.

Programmable electrical fuse with temperature gradient between anode and cathode

A method and system for modeling silicon-on-insulator shallow trench isolation stress effect is described. The method includes creating instance parameters that define dimensions of a body-tie enclosure of gate and gate-end. The instance parameters are added to a netlist. The netlist and a lookup table are used to generate a mobility multiplier. The mobility multiplier is added to the netlist and a circuit simulation program runs the netlist having the instance parameters and the mobility multiplier.

Modeling silicon-on-insulator stress effects

A method of forming a body-tie. The method includes forming the body-tie during an STI scheme of an SOI process. During the STI scheme, a first trench is formed. The first trench stops before a buried oxide layer of the SOI substrate. The first trench may determine a height of body tie that is shared between at least two FETs. A second trench may also be formed within the first trench. The second trench stops in the SOI substrate. The second trench defines the location and shape of a body-tie. Once the location and shape of the body-tie are defined, an oxide is deposited above the body-tie. The deposited oxide prevents certain implants from entering the body tie. By preventing these implants, a source and a drain implant may be self-aligned to the source and drain areas without requiring the use of the photoresist mask to shield the body tie regions from the source and drain implant.

Method of forming a body-tie

Behaviors of a transistor during a dose rate event can be modeled using a circuit simulation software package. A subcircuit model replaces a transistor in a circuit design to be simulated. The subcircuit model can be in the form of a schematic-based representation or a netlist. The subcircuit model provides a model of a source junction and a drain junction in the transistor during the dose rate event. The subcircuit model also includes the size of the transistor being replaced and the dose rate of the dose rate event. Once the transistor is replaced with the subcircuit model, a dose rate simulation may be performed to determine the dose rate hardness of the circuit design.

Simulating a dose rate event in a circuit design

A method for incorporating magnetic materials in a semiconductor manufacturing process includes manufacturing a semiconductor device including interlayers and dielectric layers, depositing a magnetic layer above a semiconductor device and forming metallized contacts for connecting interlayers of the semiconductor device. With the method of the present invention, the deposition of the magnetic material is integrated with the semiconductor manufacturing process.

Method of incorporating magnetic materials in a semiconductor manufacturing process

A varactor has a plurality of alternating P&#x2212; wells and N+ regions formed in a silicon layer. Each of the P&#x2212; wells forms a first N+/P&#x2212; junction with the N+ region on one of its side and a second N+/P&#x2212; junction with the N+ region on the other of its sides. A gate oxide is provided over each of the P&#x2212; wells, and a gate silicon is provided over each of the gate oxides. The potential across the gate silicons and the N+ regions controls the capacitance of the varactor.

Varactor with improved tuning range

A semiconductor device includes first and second polysilicon areas on a chip. The first polysilicon area corresponds to circuit elements of the semiconductor device. At least some of the first polysilicon corresponds to polysilicon gates. At least some of the second polysilicon area comprises contacts of the semiconductor device. Metal covers the polysilicon contacts.

Gate length control for semiconductor chip design

A magnetic sensor device formed using SOI CMOS techniques includes a substrate, a silicon oxide layer and in some cases a plurality of gated regions. A first terminal is located between two innermost gated regions and supplies a supply voltage. A second and a third terminal, each of which is located between two adjacent gated regions other than the two innermost gated regions, output positive and negative Hall voltages. By appropriately controlling a bias voltage to the gated regions, small changes in a magnetic field induces larger currents in channel regions under the gated regions, which, in turn, results in detectable Hall voltages.

Magnetic sensor integrated with CMOS

A method is provided to form a LOCOS isolation in a CMOS SOI device. The SOI has a top silicon layer, a bottom silicon layer, and an insulation layer between the top and bottom silicon layers. An oxide layer is formed over the top silicon layer, and an LPCVD layer is deposited over the oxide layer. A photoresist is provided over the LPCVD layer that exposes a localized area of the LPCVD layer. The LPCVD layer and the oxide layer are etched away through the localized area to expose the top silicon layer. The silicon in the top silicon layer is etched so as to form a recess in the top silicon layer. The photoresist is removed and an isolation oxide is grown over the silicon in the recess so that the silicon in the recess is fully oxidized.

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Independence, MN, United States of America

Eric E Vogt