Motorola Corporation

Eric E Quintana

Daniel T Marquette

Christopher Neal Hinds

William B Ledbetter, Jr

Russell A Reininger

Ralph C McGarity

Eric V Fiene

Robin W Edenfield

Van B Shahan

A data processing system (10) has a circuit for determining floating point exponents for divide operations and square root operations. The circuit has two input multiplexers (26 and 28) which provide exponent information or constants to an adder (30). The exponent information and constants are processed by the adder (30) to output three possible exponent values for either a divide operation or a square root operation. The three possible exponent values are stored in three registers (34, 36, and 38). A multiplexer (40) used mantissa rounding and normalizing information to determine which exponent of the three possible exponent values are correct for the current floating point calculation.

Method and apparatus for calculating floating point exponent values

A method and apparatus for detecting and completing floating point operations involving special floating point operands is performed in parallel, via a circuit (24), to the operation of at least one floating point mathematical unit (18, 20or 22). The floating point control (30) along with registers (14 and 16) provide floating point operands and floating point control to the mathematical units (18, 20, and 22). If the mathematical units (18, 20, and 22) cannot perform a proper floating point calculation because of the presence of a special operand, then the circuit (24) will detect the special operand and complete the floating point operation in a proper manner by communicating with the floating point control unit (30).

Parallel method and apparatus for detecting and completing floating

A data processor having a serialization attribute on a page basis is provided. A set of page descriptors and transparent translation registers encode the serialization attribute as a cache mode. The data processor is a pipelined machine, having at least two function units, which operate independently of each other. The function units issues requests, for access to information stored in an external memory, to an access controller. The access controller serves as an arbitration mechanism, and grants the requests of the function units in accordance with the issuance order of the requests by the function units. When the memory access is marked serialized in the page descriptor, an access controller postpones the serialized access, until the completion of all pending memory accesses in the instruction sequence. All pending requests are then completed in a predetermined order, independent of the issuance order of the requests made by the function units, and all appropriate exception processing is completed. The postponed serialized access is then completed.

Memory access serialization as an MMU page attribute

Growing community of inventors

Austin, TX, United States of America

Eric E Quintana