Xilinx, Inc.

Eric E Edwards

Wayne Edward Wennekamp

Schuyler E Shimanek

Weiguang Lu

Roy D Darling

Stephen M Trimberger

Steven P Young

Brian C Gaide

Thomas James Davies

Phillip A Young

Paul-Hugo Lamarche

Steven T Reilly

Joe Eddie Leyba, Ii

Jesse H Jenkins, Iv

Ting Lu

Jason J Moore

Shankar Lakkapragada

James A Walstrum, Jr

Kam-Wing Li

Thomas J Davies

Brendan K Bridgford

Frank C Wirtz, Ii

Charles D Laverty

Philip A Young

Thomas P LeBoeuf

Joe Eddie Ii Leyba

A method of processor operation using an integrated circuit (IC) can include loading encrypted program code into the IC through a configuration port of the IC and decrypting the encrypted program code using configuration circuitry of the IC. Decryption of the encrypted program code can result in decrypted program code which can be provided to a target destination.

Secure processor operation using integrated circuit configuration circuitry

A method of regulating a supply voltage (V) provided to a load circuit. The method can include generating at least one reference voltage (V, V, V) having a negative voltage-temperature coefficient. The method further can include applying the reference voltage as a bias voltage (V) to a current sink that is electrically coupled in parallel with a path of a leakage current (I) drawn by the load circuit. A related voltage regulator can include a current sink that is electrically coupled in parallel with a path of a leakage current drawn by a load circuit, and a bias control circuit that generates at least one reference voltage having a negative voltage-temperature coefficient and applies the reference voltage as a bias voltage to a current sink.

Regulating a supply voltage provided to a load circuit

A method of loading configuration data within an integrated circuit that includes multiple dies is disclosed. The method can include receiving configuration data in encrypted form within a first die of the multiple dies of the integrated circuit and decrypting the configuration data within the first die to generate configuration data in unencrypted form. A portion of the configuration data in unencrypted form can be distributed from the first die to each other die of the multiple dies through an interposer to which each die is attached.

Decryption of configuration data for multi-die integrated circuits

An embodiment of an integrated circuit (IC) is described. This embodiment of the IC includes an interposer; a first die on an interposer, where the first die generates a global signal propagated through the interposer; and a second die on the surface of the interposer and coupled to the global signal. The first die and the second die each is configured to implement a same operating state concurrently in response to the global signal.

Configuration of a multi-die integrated circuit

In one embodiment of the invention, a method is provided for protecting against attacks on security of a programmable integrated circuit (IC). At least a portion of an encrypted bitstream input to the programmable IC is decrypted with a cryptographic key stored in the programmable IC. A number of failures to decrypt the encrypted bitstream is tracked. The tracked number is stored in a memory of the programmable IC that retains the number across on-off power cycles of the programmable IC. In response to the number of failures exceeding a threshold, data that prevents the decryption key from being used for a subsequent decryption of a bitstream is stored in the programmable IC.

Method and integrated circuit for protecting against differential power analysis attacks

A system for uniform power regulation of an integrated circuit is disclosed. In each of a plurality of regions, the system includes a comparison circuit having a first input coupled to receive a reference voltage and a second input coupled to receive a feedback voltage. The comparison circuit provides a gating voltage to a driver circuit that is coupled to a first supply voltage. The driver circuit is configured to provide a regulated voltage responsive to the gating voltage. A feedback adjustment circuit is configured to trim the regulated voltage by a region-specific trim value and output the trimmed regulated voltage as the feedback voltage on the output.

Uniform power regulation for integrated circuits

A method of configuring an integrated circuit (IC) can include receiving configuration data within a master die of the IC. The IC can include the master die and a slave die. A master segment and a slave segment of the configuration data can be determined. The slave segment of the configuration data can be distributed to the slave die of the IC.

A method of synchronizing transitions between voltage sources that are used to provide a supply voltage. A first control signal (CS) that indicates whether to initiate a first transition from a first voltage source to a second voltage source to provide the supply voltage (V). When the first control signal indicates to initiate a first transition from a first voltage source to a second voltage source to provide the supply voltage, the first voltage source can be deactivated from providing the supply voltage. In addition, the first voltage source can be pre-biased with a voltage pre-bias to facilitate a second transition from the second voltage source to the first voltage source. Further, the second voltage source can be activated to provide the supply voltage.

Synchronizing transitions between voltage sources used to provide a supply voltage

A method and apparatus is provided to enhance the power-up sequence for integrated circuits (ICs) that contain memory cells having single-ended data inputs with no local reset function. During a power-up sequence, the logic levels that are applied to the data, address, and power inputs of the memory cell are restricted to particular magnitudes by a power-on reset (POR) state machine. First, the data input of the memory cell is held to a logic low value while an address signal of the memory cell is allowed to be asserted to a logic high value in conjunction with activating a power supply that provides operational power to the IC. Next, the address input to the memory cell ramps up to full logic high value, while the regulated power supply to the memory cell array is held low. The regulated power supply then ramps up to an operational level to bias the memory cell into a known logic state.

Apparatus and method for memory cell power-up sequence

An integrated circuit system () includes a memory array () storing a configuration data set to configure an integrated circuit. The integrated circuit () includes a configuration memory () and a configuration controller state machine (). The configuration controller state machine operates so as to read a read-check signature at a read-check address of the memory array () and to compare the read-check signature with a standard signature stored in the integrated circuit (). If the read-check signature passes the comparison, the configuration controller state machine () loads the configuration data set from the memory array to the configuration memory () of the integrated circuit.

Non-volatile memory read-check

A method of validating a bitstream loaded into a circuit having a programmable circuit is disclosed. According to one embodiment, the method comprises steps of loading a configuration bitstream comprising an error detection command at an input of the circuit; decoding the bitstream; providing a signal indicating that an error detection should be performed to a state machine when an error detection command has been decoded; and restarting the loading of the configuration bitstream if the signal has not been received. A device having a programmable circuit is also disclosed.

Circuit having a programmable circuit and method of validating a bitstream loaded into a programmable device

Method and apparatus for providing secure programmable logic devices is described. One aspect of the invention relates to securing a programmable logic device having instruction register logic coupled to control logic via an instruction bus. A non-volatile memory is provided for storing at least one security bit for at least one instruction associated with the programmable logic device. Gating logic is provided in communication with the non-volatile memory and at least a portion of the instruction bus. The gating logic is configured to selectively gate decoded instructions transmitted from the instruction register logic towards the control logic based on state of the at least one security bit.

Method and apparatus for providing secure programmable logic devices

Multiple configurations are provided for a programmable logic device (PLD), such as a field programmable gate array (FPGA), when connected to a serial peripheral interface programmable read only memory (SPI PROM) by using a programmable SPI address register incorporated into a SPI state machine of the PLD. A read command followed by a first address corresponding to first configuration data is sent from the SPI address register of the SPI state machine of the PLD to the SPI PROM. Data starting at the first address in the SPI PROM is then read by the PLD from the SPI PROM along with a second address corresponding to second configuration data. The first configuration data is stored in the PLD memory, and the second address is stored in the SPI address register. These steps may be repeated for subsequent boots of the PLD for additional configurations of the PLD.

Programmable logic device multi-boot state machine for serial peripheral interface (SPI) programmable read only memory (PROM)

A programmable device having a multi-boot capability is described. The programmable device may initially load first configuration data for configuring programmable resources of the device. Thereafter, a multi-boot operation may be triggered, causing the device to reconfigure and load second configuration data. Prior to loading the second configuration data, the device may store status information. In some cases, further multi-boot operations may be triggered for loading other configuration data.

Multi-boot configuration of programmable devices

System and apparatus for data validation is described. An initialization controller includes an initialization state machine. The initialization state machine is configured to cause configuration data to be transferred from memory internal or external to the integrated circuit to other memory internal to the integrated circuit. The configuration data is stored in the integrated circuit, read back from storage in the integrated circuit, and compressed by the integrated circuit after being read back. The configuration data is compressed into a signature, which may be compared with an expected result for the signature.

Growing community of inventors

Albuquerque, NM, United States of America

Eric E Edwards