Xilinx, Inc.

Mosys, Inc.

Rambus Inc.

Magnalynx, Inc.

Cadence Design Systems, Inc.

Eric Douglas Groen

Charles Walter Boecker

William C Black

Scott Alan Irwin

Aaron Hoelscher

Andrew G Jenkins

Joseph Neil Kryzak

Matthew Shafer

David Black

Roxanne T Vu

Michael J Gaboury

Yiqin Chen

Scott A Irwin

Joseph N Kryzak

Aaron J Hoelscher

A current-mode transmitter amplifies a differential input signal to a differential, current-mode output signal. A split-input, current-mode-logic stage produces small, analog signals to limit switching currents and thus power consumption and power-supply noise. These small, analog signals are driven through a source-follower stage to reduce loading and shift the common-mode voltage to a desired level. A switched-current-source H-bridge driver combines differential outputs from the source-follower stage to provide an amplified differential output current. The output swing from the H-bridge driver is controlled by the voltage level from the source follower and derived from a replica-bias structure.

Direct-switching h-bridge current-mode drivers

Disclosed is a system where indicators of the relative phase differences between combinations of clocks in a multi-phase clock system are developed and/or measured. These indicators convey information regarding which phase difference between a given pair of the clocks is greater than (or less than) the phase difference between another pair of the clocks. This information is used to sort/rank/order phase differences between the various combinations of pairs of clocks according to their phase differences. This ranking is used to select the pair of clocks to be adjusted.

Adjustment of multi-phase clock system

In one embodiment, a voltage mode driver circuit includes a first voltage adjusting circuit configured to provide an adjustable first pseudo-supply voltage to a first node based on a first supply voltage, including generating the first pseudo-supply voltage based on a first reference voltage and feedback from the first node. In this embodiment, the voltage mode driver circuit includes switching circuitry configured to selectively couple one of the first node or a second node to a first differential output terminal and a different one of the first node or the second node to a second differential output terminal based on a data signal. In this embodiment, the voltage mode driver circuit includes a current mode emphasis driver configured to selectively couple one of the first differential output terminal or the second differential output terminal to a first set of one or more current supplies and a different one of the first differential output terminal or second differential output terminal to a second set of one or more current supplies, based on one or more emphasis signals.

Hybrid driver circuit

A hybrid output driver includes a voltage mode main driver having an adjustable differential output voltage swing, and a current mode emphasis driver. Differential output voltage swing is adjusted by controlling the resistance of a first adjustable resistor coupled to a first voltage supply terminal, and the resistance of a second adjustable resistor coupled to a second voltage supply terminal. Resistances of the first and second adjustable resistors are adjusted by modifying a number of resistors connected in parallel. A calibration process measures the actual resistance of a similar resistor, and uses this resistance measurement to determine the number of resistors to be connected in parallel to provide the desired resistance. The current mode emphasis driver sources/sinks currents to/from differential output terminals of the hybrid output driver in response to an emphasis signal. These currents are selected in view of the selected differential output voltage swing and selected emphasis level.

Pseudo-supply hybrid driver

The present disclosure is generally directed to a method and apparatus to communicate data between two or more semiconductor devices. In an embodiment, a method includes synchronizing a master device with a slave device, where the master device includes a semiconductor device. Synchronizing includes transmitting a first synchronization marker data pattern via a first serial interface from the master device at a first time, and receiving a second synchronization marker data pattern via a second serial interface at the master device at a second time in response to transmitting the first synchronization marker data pattern. Synchronizing also includes determining, based at least in part on the first time and the second time, a third time when a reply is to be received by the master device in response to a request transmitted from the master device to the slave device.

Method and apparatus to encode and synchronize a serial interface

A device and a method for processing high data rate serial data includes circuitry for recovering a clock based on the high data rate input data stream and for providing the recovered clock to a circuit portion, for example, a portion of a field programmable gate array fabric, to enable the circuit portion to use either a reference clock or the recovered clock for subsequent processing. The invention specifically allows for different circuitry portions to utilize different clocks, including different recovered clocks, for corresponding functions that are being performed. Applications for the present invention are many but include multi-gigabit transceiver, switching devices, and protocol translation devices. More generally, the device and method provide for application specific clock references to be utilized in order to minimize or eliminate timing mismatch in serial data processing.

MGT/FPGA clock management system

An analog front-end having built-in equalization includes a control module and a tunable gain stage. The control module is operably coupled to provide a frequency response setting based on a channel response of a channel providing high-speed serial data to the analog front-end. The tunable gain stage includes a frequency dependent load and an amplifier input section. The frequency dependent load is adjusted based on the frequency response setting. The amplifier input section is operably coupled to the frequency dependent load and receives the high-speed serial data. In conjunction with the frequency dependent load, the amplifier input section amplifies and equalizes the high-speed serial data to produce an amplified and equalized serial data.

Analog front-end having built-in equalization and applications thereof

The present disclosure is generally directed to a method of communicating data between two or more semiconductor devices. Serial interfaces using the method have a reduction in latency compared to conventional serial interfaces. The method enables features needed for a serial interface, such as limited run lengths and recognizable data boundaries to establish alignment. In addition, a method for synchronizing two or more semiconductor devices through serial interfaces has been presented. This is done by passing a marker data pattern through the system.

Method of encoding and synchronizing a serial interface

A programmable logic device includes a plurality of programmable multi-gigabit transceivers, programmable logic fabric, and a control module. Each of the plurality of programmable multi-gigabit transceivers is individually programmed to a desired transceiving mode of operation in accordance with a plurality of transceiver settings. The programmable logic fabric is operably coupled to the plurality of programmable multi-gigabit transceivers and is configured to process at least a portion of the data being transceived via the multi-gigabit transceivers. The control module is operably coupled to produce the plurality of transceiver settings based on a desired mode of operation for the programmable logic device.

Programmable logic device including programmable multi-gigabit transceivers

A device and a method for processing high data rate serial data includes circuitry for recovering or generating a clock based with varying amounts of phase noise or jitter based upon a particular application. To achieve the foregoing, regulated and unregulated power are selectively provided to the circuitry for recovering a clock, to the circuitry for generating a transmission clock, and to any other circuitry having different tolerance levels for jitter and phase noise. Each power regulator comprises a current supply module and voltage regulator module. The current supply module provides one of a plurality of selectable output current levels into an output node of the regulator. The voltage regulator module having selectable voltage divider ratios at a first input of a comparator regulates an amount of current the device sinks from the output node to adjust the output voltage.

Programmable on chip regulators with bypass

A receiver termination network is included in a high-speed receiver that also includes a receiver analog front-end and a data recovery module. The receiver termination network includes a DC matched termination circuit and an AC coupled bias circuit. The DC matched termination circuit is operably coupled to provide a termination of a transmission line coupling the high-speed receiver to a transmission source and to receive high-speed data via the transmission line. The AC coupled bias circuit is operably coupled to provide a common mode reference and to high-pass filter the high-speed data to produce filtered high-speed data. The receiver analog front-end is biased in accordance with the common mode reference and is operably coupled to amplify the filtered high-speed data to produce amplified high-speed data.

Receiver termination network and application thereof

A Transmit line driver with selectable pre-emphasis and driver signal magnitudes comprises a primary current driver for setting a primary current level and a pre-emphasis current driver that provides an additional amount of current that is superimposed with or added to the primary current level produced by the primary current driver. The pre-emphasis current has either negative or positive magnitude based upon a pre-emphasis signal logic state. A first current selection module defines a reference signal that is used to select the primary current driver output signal magnitude in a first current mirror, while a second current selection module is used to define a second reference signal that selects a pre-emphasis current driver signal magnitude in a second current mirror. Logic generates a binary signal to both the first and second current selection modules to select the current levels as well as the pre-emphasis signal.

DAC based driver with selectable pre-emphasis signal levels

A high frequency latch comprising a latch and a plurality of buffers coupled to peak load circuitry produces a peak response at a desired frequency of operation as well as isolating each high frequency latch output of a plurality of outputs to substantially reduce the effects of a kickback signal coupled into the latch output. The peaked load circuitry comprises selectable resistive elements and selectable capacitive elements coupled as a high pass filter to change the bias on a saturation region MOSFET configured as an active load. The high pass filter produces positive feedback on the saturation region MOSFET to increase the bias at high frequencies thereby producing an increased response at a desired operating frequency.

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Ankeny, IA, United States of America

Eric Douglas Groen