Nxp B.v.

Koninklijke Philips Corporation N.V.

Entropic Communications, Inc.

Trident Microsystems (far East) Ltd.

Eric Desmicht

Hugues De Perthuis

Stéphane Mutz

Christophe Tison

Thierry Nouvet

The invention relates to a chip for processing a content, comprising at least a microprocessor. Said chip includes an integrated non-volatile programmable memory for storing protection data and protected data, said protection data being intended to be used for authorizing/denying access to said protected data by said microprocessor under execution of a program. The invention allows to protect program and data dedicated to a chip-integrated conditional-access system and to protect features as external connections and downloaded data directly on the chip.

Chip integrated protection means

The present invention relates to a video processing device for processing data corresponding to a sequence of pictures according to a predictive block-based encoding technique. Said device comprises a processing unit () including a reconstruction circuit () for reconstructing pictures from decoded data and an external memory () for storing reference pictures delivered by the reconstruction circuit. The processing unit further comprises a memory controller () for controlling data exchange between the processing unit and the external memory, a cache memory () for temporarily storing data corresponding to a prediction area, said data being read out from the external memory via the memory controller, and a motion compensation circuit () for delivering motion compensated data to the reconstruction circuit on the basis of the prediction area read out from the cache memory.

Video processing device with low memory bandwidth requirements

The invention relates to a functional system comprising a set of functions (F, F') which are to access a collective resource (RSRC), the system including an interface (INT) arranged to implement an access scheme (AS) including at least one state (I) defined by an order of priority for an arbitration according to which the functions (F, F&#x2032;) can access the collective resource (RSRC), the state (I) being characterized in that, for at least one set of at least two functions (F), the access possibilities in read mode (F_R) and the access possibilities in write mode (F_W) have different priority levels, the access possibilities in read mode having consecutive priority levels higher than the priority levels of the access possibilities in write mode.

Access to a collective resource in which low priority functions are grouped, read accesses of the group being given higher priority than write accesses of the group

The invention relates to a secure data processing system including an unscrambling module [DSC] disposed on a dedicated hardware part [HW] of an integrated circuit and intended to unscramble a stream of data [SP] scrambled according to a scrambling key, a module [CM] for calculating an unscrambling key [Kp] disposed on said dedicated hardware part [HW] and intended to manipulate data under the control of a so-called calculation program stored on said dedicated hardware part [HW], a processor [CPU] for in particular controlling the functioning of the unscrambling [DSC] and calculation [CM] modules. Said system also includes a read only memory [SME] disposed on said dedicated hardware part [HW] for storing a secret key [Kp]. Said calculation program includes instructions for prompting said calculation module [CM] to use said secret key [L] and at least one data item [AC[n,p] or Kpc)] coming from outside the secure data processing system, in order to calculate an unscrambling key [Kp]. The unscrambling is enabled only if the unscrambling key [Kp] corresponds to the scrambling key.

Conditional access control

Method of transferring data between a memory comprising several banks and a data processing circuit, the method comprising the steps of:

Method and system for accelerated access to a memory

The invention relates to a method of detecting a watermark W, formed by a set of coefficients, in an information signal S, said watermark W and said information signal S being configured in the form of matrices SM M*M. The coefficients of the Fourier transform matrix of the matrix of the signal TSM and the coefficients of the Fourier transform matrix of the watermark matrix TWM are used in a calculation step CAL of the inverse transform matrix of the multiplication ITM of the transform matrix of the signal TSM and of the transform matrix of the watermark TWM, said calculation CAL being produced in sequences which each result in obtaining I columns of the inverse transform matrix of the multiplication, where M is a multiple of I and different from I. Said I columns are stored in a memory called internal memory and the detection step DET of the watermark is achieved with each sequence by detection of peaks of each set of the I columns while said I columns are present in the internal memory. The invention permits the use of a small-size internal memory.

Optimized detection of a watermark in an information signal

Access by a function to a collective resource is controlled by requiring that the function waits for a minimum number of clock cycles CLK called latency [LAT] between two successive accesses of the function. The function is further required to wait a number of cycles called penalty [PEN] which is higher than the latency between two successive accesses when a given number of successive accesses separated in time by at least the value of the latency has taken place beforehand. Registers [REG, REG] are decremented (or incremented) with each clock cycle and incremented (or decremented) with each access of the function to the collective resource. Tests [T, T, T] are made with the contents of the registers to authorize [GRT] the access to the collective resource.

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Caen, France

Eric Desmicht