France Telecom

La Poste

Sgs-Thomson Microelectronics S.a.

Gemplus Card International

France Telecom Etablissement Autonome De Droit Public

France Telecom Sa

Etat Francais Represente Par Le Ministre Des Postes

Eric Depret

Philippe Hiolle

Michel Mirouze

Béatrice Parfait

Laurent Sourgen

Jean-Claude Pailles

Yves Thorigne

Philippe Maes

Philippe Gallay

Beatrice Parfait

To activate an interactive multimedia station (BN) providing facilities of a mobile office to a user of a mobile radio terminal (TM), the mobile terminal (TM) signals its presence in the vicinity of the station (BN), either by local radio link to the station itself, or by short messages to a management server (SB) when the terminal is a radiotelephone. An identifier of the terminal is transmitted from the station (BN) to the management server, or to a location recorder of the radiotelephony network (RR) to activate the station after validating the identifier.

Activating an interactive multimedia terminal

The balance or a portion of the balance associated with a prepaid card with or without a microcircuit is paid into a balance portion collection server, as a donations to charities, after setting up a call between a terminal and the server and after confirmation of the payment by the user at the terminal to increment a counter with the balance or balance portion. In another embodiment, balance portions are paid cyclically into the server or into a connection unit as and when a telephone call runs.

Payment to charities with prepaid card

Smart card payment process. The card in particular contains an irreversible counter, a balance and a certificate proving the integrity of the preceding informations. The content of the card can only be updated by terminals knowing, the calculation secrets of the certificate. By means of the irreversible counter which intervenes in the calculation of the certificate, it is not possible to reload into the card a prior content (balance/certificate), because such a reloading requires the incrementation of the counter, which renders null and void the prior certificate.

Smart card updating process

An integrated circuit for a passive unit counting memory card comprises p levels (10, 11, 12) of data counting memory. The levels contain corresponding numbers of cases n.sub.1 . . . n.sub.p, a write operation being achieved in a case of an upper rank level each time all the cases of the lower rank level have been enabled, the cases of the lower levels then being erased. The circuit comprises p-1 ghost levels (21, 22) identical to the p-1 upper rank levels of the p counting levels. The addressing logic of the ghost levels is such that the cases of ghost levels are addressed in write phase simultaneously with the cases of the corresponding counting levels and, after a write phase, are addressed in erase phase simultaneously with the cases of the levels of lower rank than the one that has just been enabled.

Data counting memory card and reader

The disclosure concerns memory cards and, more particularly, cards that are used as means of prepayment in installations for the dispensing of products and services. It is proposed to make the memory rechargeable by means of a credit counter, incrementable from outside the card, and a comparator which compares the content of this counter with that of a page counter. The page counter records the number of pages of P accounting units already used up. A no more credit signal is emitted on an external terminal when the content of the page counter reaches the content of the credit counter. A security system against the fraudulent recharging of the card is set up by an algorithm bringing into play the content of the credit counter and an identification number contained in the card.

Rechargeable prepaid memory card with both unit and page counters

A multiplier for two binary values, X and Y, comprising a very high number (q) of bits, wherein memories storing the numbers X and Y and a result register MR are provided, X being expressed as the sequence of bits (x.sub.q-1 . . . x.sub.j . . . x.sub.0), uses the algorithm consisting in sequentially carrying out from j=q-1 to j=0 the additions 2R+x.sub.j Y and each time entering the result in the result memory (MR). In this multiplier the adders are grouped into n blocks of m bits (with n.times.m=q), m being chosen so that the carry transfer time into a block is lower than a clock period. Each block comprises a first and a second line of elementary adders forming the cells (C.sub.1 to C.sub.m+1) associated with each pair of bits to be added. This multiplier is more particularly adapted for carrying out the operations XYmodN and X.sup.S modN.

Growing community of inventors

Caen, France

Eric Depret