Nintendo Co., Ltd.

Ati Technologies Ulc

Ati Technologies Inc.

Microsoft Technology Licensing, LLC

Advanced Silicon Technologies LLC

Eric Demers

Mark M Leather

Robert S Mace

Mark G Segal

Carroll Philip Gossett

Robert A Drebin

Vimal S Parikh

Derek Bosch

Yoshitaka Yasumoto

Shaun Ho

Adrian Jeday

Martin Hollis

Ian O'Donnell

Anan Nagarajan

A graphics processing circuit includes at least two pipelines operative to process data in a corresponding set of tiles of a repeating tile pattern, a respective one of the at least two pipelines operative to process data in a dedicated tile, wherein the repeating tile pattern includes a horizontally and vertically repeating pattern of square regions. A graphics processing method includes receiving vertex data for a primitive to be rendered; generating pixel data in response to the vertex data; determining the pixels within a set of tiles of a repeating tile pattern to be processed by a corresponding one of at least two graphics pipelines in response to the pixel data, the repeating tile pattern including a horizontally and vertically repeating pattern of square regions; and performing pixel operations on the pixels within the determined set of tiles by the corresponding one of the at least two graphics pipelines.

Dividing work among multiple graphics pipelines using a super-tiling technique

The present invention is a unified shader unit used in texture processing in graphics processing device. Unlike the conventional method of using one shader for texture coordinate shading and another for color shading, the present shader performs both operations. The unified shader uses the same precision for both texture coordinate and color shading, thus simplifying the complexity of programming for two separate conventional shaders with different levels of precision. Furthermore, the present invention uses enhanced scheduling logic to perform indirect texture and bump mapping in a single first-in, first-out (FIFO) memory structure and avoids the problems associated with large FIFOs with buffer registers found in conventional shaders. In one embodiment, a plurality of ALU-memory pairs are synchronized to form a plurality of pipelines to execution shading instructions. In another embodiment, a plurality of unified shaders are synchronized and connected together to processing shading operations concurrently.

Unified shader

A graphics processing circuit includes an anti-aliasing and stippling circuit operative to provide a primitive texture coordinate set in response to vertex data, the anti-aliasing and stippling circuit performing anti-aliasing operations, in parallel, with at least one appearance attribute determination operation on the vertex data, a rasterizer, coupled to the anti-aliasing and stippling circuit, operative to generate a pixel texture coordinate set in response to the primitive texture coordinate set, and apply an appearance value to a pixel defined by the pixel texture coordinate set, and a texture circuit, coupled to the rasterizer, operative to retrieve the appearance value from a corresponding one of a plurality of textures in a multi-texture map in response to the pixel texture coordinate set, the multi-texture map including data representing point, line and polygon texture data.

Apparatus for generating anti-aliased and stippled 3d lines, points and surfaces using multi-dimensional procedural texture coordinates

The present invention relates to a parallel pipeline graphics system. The parallel pipeline graphics system includes a back-end configured to receive primitives and combinations of primitives (i.e., geometry) and process the geometry to produce values to place in a frame buffer for rendering on screen. Unlike prior single pipeline implementation, some embodiments use two or four parallel pipelines, though other configurations having 2^n pipelines may be used. When geometry data is sent to the back-end, it is divided up and provided to one of the parallel pipelines. Each pipeline is a component of a raster back-end, where the display screen is divided into tiles and a defined portion of the screen is sent through a pipeline that owns that portion of the screen's tiles. In one embodiment, each pipeline comprises a scan converter, a hierarchical-Z unit, a z buffer logic, a rasterizer, a shader, and a color buffer logic.

Parallel pipeline graphics system

The embodiments of the present invention are a method and apparatus to perform anti-aliasing using multi-sampling on a non-power-of-two pixel grid. Using the present invention with 6 sample multisampling gives the same visual antialiasing quality as 8 samples using a prior art technique but uses less memory. A non-power-of-two equally spaced sample from a conventional grid of size N&#xd7;N, where N is 12 can be chosen using the present invention. A scan conversion to determine the set of pixels covered by a polygon is performed in two parts. According to one embodiment, the present invention can multiply and divide by 'N' in order to multisample an image using samples per pixel chosen from a N&#xd7;N sub-sample grid, where 'N' is not necessarily a power of 2. The present invention performs the divide by &#x201c;N&#x201d; step, where the step is achieved using a quick divide by 3 or 12 technique.

Method and apparatus for sampling on a non-power-of-two pixel grid

A graphics system including a custom graphics and audio processor produces exciting 2D and 3D graphics and surround sound. The system includes a graphics and audio processor including a 3D graphics pipeline and an audio digital signal processor. Emboss style effects are created using fully pipelined hardware including two distinct dot-product computation units that perform a scaled model view matrix multiply without requiring the Normal input vector and which also compute dot-products between the Binormal and Tangent vectors and a light direction vector in parallel. The resulting texture coordinate displacements are provided to texture mapping hardware that performs a texture mapping operation providing texture combining in one pass. The disclosed pipelined arrangement efficiently provides interesting embossed style image effects such as raised and lowered patterns on surfaces.

Method and apparatus for efficient generation of texture coordinate displacements for implementing emboss-style bump mapping in a graphics rendering system

A graphics processing circuit includes a line end generation circuit operative to generate line aligned end cap data in response to primitive data; and a rasterizer, coupled to the line end generation circuit, operative to generate pixel data representing a line to be rendered, the pixel data including the line aligned end cap data. A graphics processing method includes receiving primitive data for a line to be rendered, the primitive data including start endpoint data and stop endpoint data, determining the height and width of the line in screen space, determining line end cap orientation with respect to the line to be rendered, and determining vertices that define the line to be rendered, wherein the vertices define end caps aligned with the line to be rendered.

Apparatus for generating efficient wide-line ends

A graphics system including a custom graphics and audio processor produces exciting 2D and 3D graphics and surround sound. The system includes a graphics and audio processor including a 3D graphics pipeline and an audio digital signal processor. An additional matrix multiplication computation unit connected in cascade with a modelview matrix computation unit can support a piecewise linear version of skinning for skeletal animation modeling. The normalizer connected between the cascaded matrix multiplication computation units can provide normalization to avoid distorted visualization. The additional matrix multiplication computation unit can be used for applications other than skeletal animation modeling (e.g., environment mapping).

Low cost graphics with stitching processing hardware support for skeletal animation

A graphics system including a custom graphics and audio processor produces exciting 2D and 3D graphics and surround sound. The system includes a graphics and audio processor including a 3D graphics pipeline and an audio digital signal processor. Cartoon lighting and other non-photorealistic effects can be produced by using a lighting calculation to produce a parameter other than color or opacity for use in a later modification of a color or opacity value. In more detail, the example embodiment uses the lighting calculation to generate texture coordinates used in a texture mapping operation. The texture mapping operation allows lighting computation results to select between brush strokes for cartoon lighting and other effects. The resulting dynamic cartoon lighting animation can be performed on a low cost platform such as a home video game system or personal computer.

Achromatic lighting in a graphics system and method

A processor for computer graphics calculations comprising an entire graphics engine in a single integrated circuit. The processor includes a transform mechanism adapted to compute transforms for the computer graphics calculations. The transform mechanism includes a transformation element adapted to compute transforms using a dot product operation. The transform mechanism of the processor also includes a perspective division element, a color unit for lighting calculations, a scaling element for multiplication operations, and a look-up table containing mathematical functions used by the computer graphics calculations. The processor also includes a raster unit coupled to the transform mechanism, a texture unit coupled to the raster unit, and a shader unit coupled to the texture unit.

Growing community of inventors

Palo Alto, CA, United States of America

Eric Demers