Intel Corporation

Eric Dehaemer

Krishnakanth Venkata Sistla

Ankush Varma

Vivek Garg

Ian M Steiner

Matthew M Bace

Adwait Purandare

Efraim Rotem

Eliezer Weissmann

Min Huang

Andrew J Herdrich

Avinash N Ananthakrishnan

Alexander Gendler

Nadav Shulman

Nir Rosenzweig

Dean A Mulla

Malini Krishnan Bhandaru

Nikhil Gupta

Baskaran Ganesan

Scott P Bobholz

Nazar Syed Haider

Ariel Szapiro

Chris Poirier

William Johnson Bowhill

Ripan Das

Yogesh Bansal

Nimrod Angel

Ido Melamed

Suresh Chemudupati

Aman Sewani

Zhiguo Wang

Elkana Korem

Arye Albahari

Nilanjan Palit

Nir Misgav

Rupal Parikh

Vinod Ambrose

Ujjwal Gupta

Joseph R Doucette

Pavithra Sampath

A Leonard Brown

Stanley Chen

Nikethan Shivanand Baligar

Yin-Lung Lu

Seow Fung Ooi

Harjinder Hullon

Stephen Wang

Dorit Shapira

Shruthi Venugopal

Phani Kumar Kandula

Michael Tulanowski

Timothy Yee-Kwong Kam

Stephen Paul Haake

Joseph Doucette

Seow Ooi

Deif Atallah

Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.

Hierarchical power management apparatus and method

A local power control arbiter is provided to interface with a global power control unit of a processing platform having a plurality of processing entities. The local power control arbiter controls a local processing unit of the processing platform. The local power arbiter has an interface to receive from the global power control unit, a local performance limit allocated to the local processing unit depending on a global power control evaluation and processing circuitry to determine any change to one or more processing conditions prevailing in the local processing unit on a timescale shorter than a duration for which the local performance limit is applied to the local processing unit by the global power control unit and to select a performance level for the local processing unit depending on both the local performance limit and the determined change, if any, to the prevailing processing conditions on the local processing unit.

Power control arbitration

In an embodiment, a processor includes a plurality of cores grouped into a plurality of clusters. The clusters are formed based on a corresponding operating voltage of each core at each of a plurality of frequencies. Each cluster includes a unique set of cores and at least one cluster includes at least two of the cores. The processor also includes a power control unit (PCU) including frequency/voltage control logic, responsive to a frequency change request for a first core of a first cluster, to determine an operating voltage for the first core from a first cluster voltage-frequency (V-F) table associated with the first cluster. The first cluster V-F table uniquely specifies a corresponding operating voltage at each of a plurality of frequencies of operation of the cores of the first cluster. Other embodiments are described and claimed.

Apparatus and method to implement power management of a processor

In an embodiment, a processor includes a plurality of cores each to independently execute instructions, and a power control unit coupled to the plurality of cores to control power consumption of the processor, where the power control unit includes a control logic to reduce a maximum operating frequency of the processor if a first number of forced performance state transitions occurs in a first time period or a second number of forced performance state transitions occurs in a second time period. Other embodiments are described and claimed.

Adaptively limiting a maximum operating frequency in a multicore processor

A processor is described that includes a processing core and a plurality of counters for the processing core. The plurality of counters are to count a first value and a second value for each of multiple threads supported by the processing core. The first value reflects a number of cycles at which a non sleep state has been requested for the first value's corresponding thread, and, a second value that reflects a number of cycles at which a non sleep state and a highest performance state has been requested for the second value's corresponding thread. The first value's corresponding thread and the second value's corresponding thread being a same thread.

Processor having per core and package level P0 determination functionality

Growing community of inventors

Shrewsbury, MA, United States of America

Eric Dehaemer