Motorola Corporation

Eric D Neely

Michael A Wells

Carlos D Obregon

Daniel T Bizuneh

Perng Hsyng

A 3 state BiCMOS output buffer (100) with power down capability has been provided. The buffer includes an input stage (102), responsive to an input signal, an output coupled to both a pull-up driver (114), and an output pull-down driver (116) wherein the drivers provide an output signal at an output of the buffer in response to the input signal. Additionally, the buffer includes a power down sense circuit (108), coupled to a power supply node (118), for turning off an output pull-up transistor (214) when the power supply node is powered down and thus eliminating leakage paths within the buffer. The buffer also includes a noise limiting circuit (112) for slowing down a high to low transition at the output of the buffer thereby reducing the switching noise of the buffer while not affecting the overall speed of the buffer.

3-state bicmos output buffer having power down capability

The present invention includes an input buffer circuit (10) having sleep mode and bus hold capability. An input section (11) of the buffer circuit is operated from an operating voltage which is lower than a supply voltage of the buffer circuit thereby minimizing the static power dissipation. Sleep mode circuitry (15, 36, 38) is included for effectively disconnecting an input signal from the rest of the buffer circuit thereby minimizing dynamic power dissipation. Bus hold circuitry (40) is included for holding the logic state appearing at an output of the input buffer circuit when the input signal is removed thereby further reducing the static power dissipation.

Input buffer circuit having sleep mode and bus hold function

A plurality of transistors (22, 23, 27) are utilized to provide a low noise high-to-low transition (40) on an output (19) of a circuit (10). The transistors (22, 23, 27) are sequentially enabled to vary a rate of change of output current thereby minimizing noise created by the high-to-low transition (40). A first transistor (22) is enabled to provide a low rate of change. Subsequently, a second transistor (23) is enabled to provide a higher rate of change. Then, just prior to disabling the second transistor (23) a third transistor (27) is enabled to provide a d.c. level.

Low noise BICMOS circuit

A TTL output driver is provided which increases the high level of the output signal thereof. The first and second emitters of a first transistor are coupled to the collector and base of a second transistor, respectively, the emitter and collector of which are coupled to the output of the TTL output driver and through a series combination of diode and resistor to a source of operating potential respectively. The output voltage is increased by reducing the base current drive of the first transistor required to achieve the desired output current.

TTL output driver having an increased high output level

A circuit for use in conjunction with an enable/disable gate of a three state logic circuit for disabling the outputs of the logic circuit during power up of the voltage supply to maintain a high impedance output state at the outputs of the logic circuits. The circuit includes a voltage level detector stage comprising a switching transistor that is held in a non-conducting state until the voltage supply reaches a predetermined potential after which the transistor is turned on and a pair of transistors configured as a current mirror with their bases coupled to the output of the switching transistor. The pair of transistors are turned on until the switching transistor is turned on to provide sufficient base current drive to a disable transistor of the enable/disable gate such that the logic circuit is disabled accordingly. An aspect of the invention is that the power up circuit draws little additional power during normal operation of the logic circuit.

Low power, three state power up circuit

A three state gate having an output capable of assuming an active high, an active low, or a high impedance state is disclosed that eliminates a glitch in the output during the transition from the high impedance state to an active high. An output means includes a first transistor for supplying current to the output and a second transistor for draining current from the output. A phase splitting means determines the conductivity of the first and second transistors. A logic means is responsive to both an input signal and an output enable signal and is coupled to the phase splitting means. The logic means includes a level setting means that insures that the second transistor is not conductive during the transition of the output from the active high to the high impedance state.

Non-inverting three state TTL logic with improved switching from a high

A three state gate having an output capable of assuming an active high, an active low, or a high impedance state is disclosed that has an enhanced transition from the active high to the active low. An output means includes a first transistor for supplying current to the output and a second transistor for sinking current from the output. A phase splitter means coupled to the output means determines the conductivity of the first and second transistors. An input means is responsive to an input signal and controls the phase splitter means. An output enable means is provided that disables both the first and second transistors for providing the high impedance output. A feedback means for enhancing the downward transition of the output signal from an active high to an active low includes a feedback transistor having a base connected to a supply voltage terminal by a resistor which can be used to vary the speed of the downward transition. A diode is coupled between the collector of the feedback transistor and the output terminal. The feedback transistor is reverse biased, except when the output signal is transitioning from the active high to the active low. A second diode is coupled between the base of the first output transistor and the collector of the feedback transistor for discharging stored base-collector capacitance of the first output transistor.

Three state gate having enhanced transition to an active low

A circuit for providing a signal which enables the high impedance state of a subsequent three state circuit includes a first circuit portion which provides current to an output node to disable the high impedance state when an input signal is in the first state and a second circuit portion which sinks current from the output node to enable the high impedance state when the input signal is in a second state. The circuit includes an input stage which is directly coupled to a transistor, which transistor simultaneously enables said second circuit portion and disables said first circuit portion when the input signal switches from said second state to said first state.

Enable gate for 3 state circuits

A data selection circuit selectively generates first and second complementary signals in response to an input signal so as to enable specific data paths and disable others. The circuit includes a non-inverting portion which generates an output signal having the same sense as the input signal, and an inverting portion which inverts the input signal. Since the non-inverting portion has an extra inverting stage within it, a diode is coupled between the inverting portion and the true output for steering base drive away from the inverting portion when the input signal makes a low to high transition. In this manner, the inverting output is prevented from going low until the non-inverting goes high.

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Mesa, AZ, United States of America

Eric D Neely