Freescale Semiconductor,inc.

Motorola Corporation

Eric D Luckowski

Shahid Rauf

Peter L G Ventzek

Douglas R Roberts

Olubunmi O Adetutu

Robert E Jones

James Kenyon Schaeffer, Iii

Bradley M Melnick

Carole C Barron

Renee Tong Mo

Srikanth Balaji Samavedam

Daniel J Jaeger

Todd Christopher Bailey

Arturo Manuel Martinez, Jr

Ying H Tsang

Amy L Child

A method and apparatus are described for fabricating metal gate electrodes () over a high-k gate dielectric layer () having a rare earth oxide capping layer () in at least the NMOS device area by treating the surface of a rare earth oxide capping layer () with an oxygen-free plasma process () to improve photoresist adhesion, forming a patterned photoresist layer () directly on the rare earth oxide capping layer (), and then applying a wet etch process () to remove the exposed portion of the rare earth oxide capping layer () from the PMOS device area.

Method of enhancing photoresist adhesion to rare earth oxides

A method and apparatus are described for fabricating single metal gate electrodes () over a high-k gate dielectric layer () that is separately doped in the PMOS and NMOS device areas () by forming first capping oxide layer () with a first dopant species on a high-k gate dielectric layer () in at least the NMOS device area and also forming second capping oxide layer () with a second dopant species on a high-k gate dielectric layer () in at least the PMOS device area, where the first and second dopant species are diffused into the gate dielectric layer () to form a first fixed charge layer () in the PMOS device area of the high-k gate dielectric area and a second fixed charge layer () in the NMOS device area of the high-k gate dielectric area.

CMOS integration with metal gate and doped high-K oxides

A method for forming a capacitor includes providing a metal-containing bottom electrode, forming a capacitor insulator over the metal-containing bottom electrode, forming a metal-containing top electrode over the capacitor insulator, and forming a dielectric-containing field modification layer over the capacitor insulator and at least partially surrounding the metal-containing top electrode. Forming the dielectric-containing field modification layer may include oxidizing a sidewall of the metal-containing field modification layer. A barrier layer may be formed over the capacitor insulator prior to forming the metal-containing top electrode.

Thin-film capacitor with a field modification layer

A metal layer etch process deposits, patterns and anisotropically etches a polysilicon layer () down to an underlying metal layer () to form an etched polysilicon structure () with polymer layers () formed on its sidewall surfaces. The polymer layer () are removed to expose an additional surface area () of the metal layer (), and dielectric layers () are formed on the sidewall surfaces of the etched polysilicon structure (). Next, the metal layer () is plasma etched to form an etched metal layer () with substantially vertical sidewall surfaces () by simultaneously charging the dielectric layers () to change plasma ion trajectories near the dielectric layers () so that plasma ions () impact the sidewall surfaces () in a more perpendicular angle to enhance etching of the sidewall surfaces () of the etched metal layer ().

Method for removing metal foot during high-k dielectric/metal gate etching

Thin-film capacitor with a field modification layer and methods for forming the same

A self-aligned magnetic clad bit line structure () for a magnetic memory element () and its method of formation are disclosed, wherein the self-aligned magnetic clad bit line structure () extends within a trench () and includes a conductive material (), magnetic cladding sidewalls () and a magnetic cladding cap (). The magnetic cladding sidewalls () at least partially surround the conductive material () and the magnetic cladding cap () is substantially recessed within the trench with respect to the top of the trench.

Self-aligned magnetic clad write line and its method of formation

A semiconductor device has a P channel gate stack comprising a first metal type and a second metal type over the first metal type and an N channel gate stack comprising the second metal type in direct contact with the a gate dielectric. The N channel gate stack and a portion of the P channel gate stack are etched by a dry etch. The etch of P channel gate stack is completed with a wet etch. The wet etch is very selective to the gate dielectric and to the second metal type so that the N channel transistor is not adversely effected by completing the etch of the P channel gate stack.

Process for forming dual metal gate structures

A self-aligned magnetic clad bit line structure ( ) for a magnetic memory element ( ) and its method of formation are disclosed, wherein the self-aligned magnetic clad bit line structure ( ) extends within a trench ( ) and includes a conductive material ( ), magnetic cladding sidewalls ( ) and a magnetic cladding cap ( ). The magnetic cladding sidewalls ( ) at least partially surround the conductive material ( ) and the magnetic cladding cap ( ) is substantially recessed within the trench with respect to the top of the trench.

A process for forming a metal-insulator-metal (MIM) capacitor structure includes forming a recess in the dielectric layer ( ) of a semiconductor substrate ( ). A first capacitor electrode ( ) is formed in the recess having a copper first metal layer ( ) with a conductive oxidation barrier ( ) formed over the first metal layer ( ). The first capacitor electrode ( ) is planarized relative to the dielectric layer ( ). An insulator ( ) is formed over the first capacitor electrode ( ) and a second capacitor electrode ( ) is formed over the insulator ( ). Forming the first capacitor electrode ( ) in the recess maintains the alignment of a periphery of the copper first metal layer ( ) with the conductive oxidation barrier ( ).

Growing community of inventors

Round Rock, TX, United States of America

Eric D Luckowski