International Business Machines Corporation

Globalfoundries Inc.

Eric D Johnson

James Stuart Dunn

Badih El-Kareh

Robert Andrew Kertis

Nicholas Theodore Schmidt

Kenneth Knetch Kieft, Iii

Sridhar Divakaruni

Michael Dean Hulvey

Albert Edson Lanpher

Anthony K Stamper

Jeffrey P Gambino

Albert Manhee Chu

Michael Joseph Zierak

Richard A Phelps

Ian McCallum-Cook

Manikandan Viswanath

William J Rensch

A high resistivity substrate final resistance test structure, methods of manufacture and testing processes are disclosed. The test structure includes spaced apart implants extending into a high resistivity wafer in at least one kerf region of the wafer. The test structure further includes contacts in direct electrical contact to each of the spaced apart implants.

High resistivity substrate final resistance test structure

Systems and methods for determining adjustable wafer acceptance criteria based on chip characteristics. The method includes measuring a density of at least one chip. The method further includes computing a difference in density between the density of the at least one chip and a density of at least one kerf structure. The method further includes calculating an offset value to modify a Wafer Acceptance Criteria (WAC) to match the density difference between the at least one chip and the at least one kerf structure. The method further includes applying the offset value to the WAC for a wafer level measurement in order to increase chip yield performance.

Systems and methods for determining adjustable wafer acceptance criteria based on chip characteristics

High-performance bipolar transistors with improved wiring options and fabrication methods therefore are set forth. The bipolar transistor includes a base contact structure that has multiple contact pads which permit multiple device layouts when wiring to the transistor. For example, a first device layout may comprise a collector-base-emitter device layout, while a second device layout may comprise a collector-emitter-base device layout. More specifically, the base contact structure at least partially surrounds the emitter and has integral contact pads which extend away from the emitter. Further, sections of the base contact structure are disposed on an insulating layer outside of the perimeter of the base region of the transistor, while other sections directly contact the base region. Specific details of the bipolar transistor, and fabrication methods therefore are also set forth.

Method of forming high performance bipolar devices with improved wiring

High performance bipolar devices with plurality of base contact regions

A high performance PNP lateral bipolar transistor is described, incorporating at least two trenches extending from the upper P.sup.- surface of a semiconductor substrate almost to a buried N.sup.+ layer. The floor of one trench is heavily N-doped to establish a connection between the buried N.sup.+ layer and an N.sup.- diffusion in the walls of the trench. When the trenches are backfilled with P.sup.+ polysilicon a lateral PNP is formed having a buried base contact.

High performance lateral PNP transistor with buried base contact

Method of forming high performance lateral PNP transistor with buried

A method of forming a low resistance path, e.g., to serve as a guard ring, in a silicon semiconductor device is disclosed. An opening is defined in an upper protective layer and an underlying lower protective layer. Normally these layers are silicon nitride and silicon dioxide, respectively. The lower protective layer is isotropically wet etched so that the upper protective layer overhangs the lower protective layer and protects a part of the silicon wafer surface. A first impurity is implanted in the exposed silicon wafer surface except in the annular area protected by the upper protective layer overhang. A silicon dioxide layer is grown on the entire exposed surface of the silicon wafer which is inherently thicker over the area where the impurity has been implanted and inherently thinner over the annular area where the impurity has not been implanted. The upper protective layer is then preferably removed. A second impurity is implanted through the annular thinner silicon dioxide layer, which optionally may be etched away, to create, e.g., a guard ring in the silicon wafer around the perimeter of the thicker silicon dioxide layer which has protected the silicon wafer from the implant.

Process for forming a self-aligned low resistance path in semiconductor

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Westford, VT, United States of America

Eric D Johnson