Cypress Semiconductor Corporation

Eric D Blom

Harold Kutz

Mark W Rouse

Warren S Snyder

Timothy John Williams

David Gordon Wright

Bert Sullam

Craig Nemecek

Greg Verge

Melany Ann Richmond

Jeffrey Erickson

Robert Walter Metzler, Jr

Xuan Nguyen

John Roy

Ba Kang Chu

A programmable system includes an input/output (I/O) pin that is configurable into multiple operational states. The programmable system further includes a memory device to store configuration data that, when provided to the I/O pin, causes the I/O pin to reconfigure into one of the operational states. When power is supplied to the system, the memory device is configured to provide the configuration data to the I/O pin prior to a system microcontroller becoming operational responsive to the power.

Configurable reset pin for input/output port

A variable reference voltage circuit for performing memory operation on non-volatile memory includes a multi-level voltage source and a selector circuit. The multi-level voltage source generates multiple voltages. The selector circuit includes a selector input and a selector output. The selector input is coupled to the multi-level voltage source to selectively couple any of the multiple voltages to the selector output. The selector output of the selector circuit is coupled to a non-volatile memory array to provide the NV memory array with a selectable program voltage for programming the NV memory array and a selectable erase voltage for erasing the NV memory array.

Variable reference voltage circuit for non-volatile memory

A method and apparatus for verifying non-volatile memory. A first transmission of data is received by a first memory of a device. The data is received by a non-volatile memory of the device. The data received by the non-volatile memory is verified by comparing it to the data in the first memory with comparison logic of the device. The verification is performed without receiving a second transmission of the data and without sending a second transmission of the data. A result is generated from the comparison.

Self verification of non-volatile memory

One embodiment of the present invention provides a method of memory management. Within the present embodiment, a page register along with supporting logic allows a mode to be selected by a processor at the same time it specifies a particular memory page. The selected mode defines what the subsequent use of the specified memory page will be. For example, this method may decrease overhead when moving between different memory pages by providing a mode that automatically returns to a previous page after a specified page has been accessed.

Memory management

A method and circuit provide a system level reset function for an electronic device. An initial reset function is provided under a low voltage condition of supply voltage, such as occur upon first energizing the electronic device. A tunable reset function is also provided, which can first be asserted at a voltage level setting less precise than that setting becomes upon tuning. Further, a boot-up reset function is provided, which provides its reset function at a voltage level setting that is set according to a calibration. Calibration can be based on data stored in a non-volatile memory, and can involve a checksum operation. The electronic device, a microcontroller for instance, is held in a reset state with any of the initial, tunable, and boot-up reset functions.

Method and circuit for providing a system level reset function for an electronic device

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Lynnwood, WA, United States of America

Eric D Blom