Unisys Corporation

Eric D Aho

Philip C Bolyn

Anthony P Gold

Michael K Benton

Mark D Luba

Daniel Heine

A system provides a cache memory coherency mechanism within a multi-processor computing system utilizing a shared memory space across the multiple processors. The system possesses a store address list for storing cache line addresses corresponding to a cache line write request issued by one of the multiple processors, a fetch address list for storing cache line addresses corresponding to a cache line fetch request issued by one of the multiple processors, a priority and pipeline module, a request tracker module and a read/write address list. The store address list and the fetch address list are queues containing result in cache lookup requests being done by the priority and pipeline module; and each entry in the store address list and the fetch address list possess status bits which indicate the state of the request.

System and method for providing L2 cache conflict avoidance

An extended data queue is added to the cache circuitry of a processor to handle extended data when the processor operates on a different architecture than the system it resides on. The extended data for each word coming into the processor is stored in the queue. If the extended data has some valid information, the word is replaced to ensure the information is not lost. If there is no valid information in the extended data, then the bits of the extended data are simply set to zero.

System and method for non-destructive handling of outsized words by a cache

The present invention provides a method and a computer system that compares a portion of a signal and information transferred from a cache memory, while the information is in transit from the cache memory. The information may be routed differently depending on the outcome of the compare. Specifically, the information may be delivered to a memory bus when it matches the portion of the signal and when the signal is a read command. Alternatively, the information may not be delivered to a memory bus when it matches the portion of the signal and when the signal is a write command. If the information does not match the portion of the signal, it may be transferred to a main memory via a memory bus. The information may be compared to the portion of the signal for a first time interval, and the portion of the signal may be compared to the information for a second time interval. The information may be transferred from the cache memory on a first clock signal, while the signal is provided by the memory bus on a second clock signal asynchronous with the first clock signal.

Method for controlling concurrent cache replace and return across an asynchronous interface

A single ASIC memory controller has full interconnectivity between various modes on the ASIC: input controller, memory controller, and output controller. The single ASIC includes an input controller section, a memory controller section, and an output controller section. The ASIC architecture is designed to allow any of the sections to be bypassed. Using the bypass mechanism, the ASIC can be combined with other like ASICs to increase system performance and capabilities without the need for ASIC redesign. The ASIC design can be used in memory subsystems that are scalable depending on user requirements.

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Phoenixville, PA, United States of America

Eric D Aho