Cirrus Logic Inc.

Eric Clay Gaalaas

John James Paulos

Xue-Mei Gong

Mark Alexander

Johann Guy Gaboriau

Vishnu Shankar Srinivasan

Dylan Alexander Hester

Jason Powell Rhode

Lei Jin

A multi-bit DAC (,) is provided as part of a digital-to-analog data converter (DAC). The multi-bit DAC is comprised of a plurality of single-bit DACs (,) which have the values thereof selected through a digital encoder (,). The digital encoder (,) performs dynamic element matching (DEM) on an input data value. The sequence of selection is performed such that the element mismatch noise response of the DAC (,) is shaped. The outputs are summed at a summing junction (,) and then filtered with a low pass filter (,). In the noise shaping response, a cyclical second order response is provided with a Data Weighted Averaging (DWA) technique wherein the outputs of the DACs are restricted to one of two states. To achieve this, select ones of the output values are changed in order to comply with this restriction, thus deviating from a uniform element selection algorithm. This provides a constrained second order response which accounts for mismatching of the DAC elements (,).

2nd order noise shaping dynamic element matching for multibit data converters

An sample rate converter for non-audio AES data channels is presented. Channel status (C) information is transferred in 192-bit blocks. Access to received C channel data blocks is allowed, before the blocks are re-transmitted at the output sample rate. This enables users to modify the data, alleviating the effect of data loss caused by different input and output sample frequencies. For U channel status information, U channel status information is transferred as 2&times;192 bit blocks like the channel status (C) scheme above, as individual information units (IUs), or as messages consisting of 129 IUs. In the latter 2 schemes, the lengths of output inter-IU filler segments or output intemessage filler segments are varied relative to the lengths of inputs inter-IU filler segments or input inter-IU message segments respectively, to compensate for the difference between the input sample frequency and the output sample frequency.

Sample rate conversion of non-audio AES data channels

Circuitry for selectively sampling a reference voltage with a capacitor 403 includes a first switch 505a for selectively coupling capacitor 403 to a source of a first reference signal during a first operating phase and a second switch 505b for selectively coupling capacitor 403 to a source of a second reference signal during a second operating phase.

Reference voltage circuitry for use in switched-capacitor applications

Digital-to-analog conversion circuitry 100 is shown including a path for processing data in a 1-bit format. First portion of an analog finite impulse response filter 300 includes pre-selected number of delay elements 301 for receiving stream of data in the 1-bit format and outputting a plurality of signals in response. A switched capacitor digital-to-analog converter 106 forms a second portion of the finite impulse response filter 301 and has a plurality of elements each receiving one of the plurality of signals as selected to effectuate a set of filter coefficients, converter 106 summing the plurality of signals and outputting an analog data stream.

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Austin, TX, United States of America

Eric Clay Gaalaas