Arm Limited

Eric Charles Quinnell

Yasuo Ishii

Abhishek Raja

Joseph Michael Pusdesris

Chris Abernathy

Michael David Achenbach

Nicholas Andrew Plante

In register renaming circuitry architectural registers specified in instructions are mapped to physical registers using a mapping table. Operations to be performed with respect to the physical registers are generated in dependence on the instructions and on the mapping table entries. When the mapping table has a mapping of a first instruction destination physical register for a first instruction destination architectural register specified in a first instruction, a second instruction specifying the first instruction destination architectural register as a second instruction source architectural register causes an adapted second operation to be generated corresponding to the second instruction using at least one first instruction source physical register as at least one second instruction source physical register. The adapted second operation incorporates a first operation corresponding to the first instruction.

Register rename stage fusing of instructions

Circuitry comprises two or more clusters of execution units, each cluster comprising one or more execution units to execute processing instructions; and scheduler circuitry to maintain one or more queues of processing instructions, the scheduler circuitry comprising picker circuitry to select a queued processing instruction for issue to an execution unit of one of the clusters of execution units for execution; in which: the scheduler circuitry is configured to maintain dependency data associated with each queued processing instruction, the dependency data for a queued processing instruction indicating any source operands which are required to be available for use in execution of that queued processing instruction and to inhibit issue of that queued processing instruction until all of the required source operands for that queued processing instruction are available and is configured to be responsive to an indication to the scheduler circuitry of the availability of the given operand as a source operand for use in execution of queued processing instructions; and the scheduler circuitry is responsive to an indication of availability of one or more last awaited source operands for a given queued processing instruction, to inhibit issue by the scheduler circuitry of the given queued processing instruction to an execution unit in a cluster of execution units other than a cluster of execution units containing an execution unit which generated at least one of those last awaited source operands.

Circuitry and method

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Austin, TX, United States of America

Eric Charles Quinnell