Intel Corporation

Eric Charles Mattson

Matthew V Metz

Jack T Kavalieros

Gilbert W Dewey

Scott Bruce Clendenning

Nazila Haratipour

I-Cheng Tung

Marko Radosavljevic

Ian A Young

Seung Hoon Sung

Uygar E Avci

Charles C Kuo

Nicole K Thomas

Chia-Ching Lin

Shriram Shivaraman

Ashish Verma Penumatcha

Siddharth Chouksey

Sou-Chi Chang

Sudarat Lee

Owen Y Loh

Devin Merrill

Jitendra Kumar Jha

Mengcheng Lu

Thoe Michaelos

Tobias Brown-Heft

Charles Mokhtarzadeh

Integrated circuitry comprising a ribbon or wire (RoW) transistor stack within which the transistors have different threshold voltages (V). In some examples, a gate electrode of the transistor stack may include only one workfunction metal. A metal oxide may be deposited around one or more channels of the transistor stack as a solid-state source of a metal oxide species that will diffuse toward the channel region(s). As diffused, the metal oxide may remain (e.g., as a silicate, or hafnate) in close proximity to the channel region, thereby altering the dipole properties of the gate insulator material. Different channels of a transistor stack may be exposed to differing amounts or types of the metal oxide species to provide a range of Vwithin the stack. After diffusion, the metal oxide may be stripped as sacrificial, or retained.

Ribbon or wire transistor stack with selective dipole threshold voltage shifter

Embodiments disclosed herein include semiconductor devices with source/drain interconnects that include a barrier layer. In an embodiment the semiconductor device comprises a source region and a drain region. In an embodiment, a semiconductor channel is between the source region and the drain region, and a gate electrode is over the semiconductor channel. In an embodiment, the semiconductor device further comprises interconnects to the source region and the drain region. In an embodiment, the interconnects comprise a barrier layer, a metal layer, and a fill metal.

Halogen treatment for NMOS contact resistance improvement

A integrated circuit structure comprises a fin extending from a substrate. The fin comprises source and drain regions and a channel region between the source and drain regions. A multilayer high-k gate dielectric stack comprises at least a first high-k material and a second high-k material, the first high-k material extending conformally over the fin over the channel region, and the second high-k material conformal to the first high-k material, wherein either the first high-k material or the second high-k material has a modified material property different from the other high-k material, wherein the modified material property comprises at least one of ferroelectricity, crystalline phase, texturing, ordering orientation of the crystalline phase or texturing to a specific crystalline direction or plane, strain, surface roughness, and lattice constant and combinations thereof. A gate electrode ix over and on a topmost high-k material in the multilayer high-k gate dielectric stack. A selector element is above the metal layer.

Multilayer high-k gate dielectric for a high performance logic transistor

Growing community of inventors

Portland, OR, United States of America

Eric Charles Mattson